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| Presentation | 2018-04-13 13:30 AES-OTR Hardware Architecture and Its Evaluation Rei Ueno, Noafumi Homma (Tohoku Univ.), Tomonori Iida (YDK), Kazuhiko Minematsu (NEC)  HWS2018-4 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper reports a hardware implementation of AES-OTR, an authenticated encryption schemes based on AES. AES-OTR is a candidate of CAESAR competition, an international competition for authenticated encryption. We propose a compact multi-core architecture for AES-OTR which utilizes its parallelizability and inverse-freeness property (i.e. the decryption logic of AES is not needed), and show implementation results on ASIC and FPGA. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Authenticated Encryption / AES-OTR / Hardware Architecture / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 118, no. 3, HWS2018-4, pp. 17-21, April 2018. | |
| Paper # | HWS2018-4 | |
| Date of Issue | 2018-04-06 (HWS) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | HWS2018-4 |
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| Conference Information | |
| Committee | HWS |
| Conference Date | 2018-04-13 - 2018-04-13 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | HWS |
| Conference Code | 2018-04-HWS |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | AES-OTR Hardware Architecture and Its Evaluation |
| Sub Title (in English) | |
| Keyword(1) | Authenticated Encryption |
| Keyword(2) | AES-OTR |
| Keyword(3) | Hardware Architecture |
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| 1st Author's Name | Rei Ueno |
| 1st Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 2nd Author's Name | Noafumi Homma |
| 2nd Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 3rd Author's Name | Tomonori Iida |
| 3rd Author's Affiliation | Y.D.K.CO., LTD (YDK) |
| 4th Author's Name | Kazuhiko Minematsu |
| 4th Author's Affiliation | NEC Corporation (NEC) |
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| Speaker | Author-1 |
| Date Time | 2018-04-13 13:30:00 |
| Presentation Time | 25 minutes |
| Registration for | HWS |
| Paper # | HWS2018-4 |
| Volume (vol) | vol.118 |
| Number (no) | no.3 |
| Page | pp.17-21 |
| #Pages | 5 |
| Date of Issue | 2018-04-06 (HWS) |
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