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Paper Abstract and Keywords
Presentation 2018-04-19 10:10
Reliability Enhancement Technique with Horizontal Error Detection and Vertical-LDPC in 3D-TLC NAND Flash Memories
Shun Suzuki, Yoshiaki Deguchi, Toshiki Nakamura, Kyoji Mizoguchi, Ken Takeuchi (Chuo Univ.) ICD2018-1
Abstract (in Japanese) (See Japanese page) 
(in English) Conventional Asymmetric Coding (AC) has been proposed for improving NAND flash memories. In this work, Horizontal Error Detection (HED), which adds the error detection algorithm to AC, and Vertical-LDPC (V-LDPC), which corrects errors without depending on the bias among pages of TLC NAND flash memories, are proposed. In addition, Cross Error Elimination (XEE) ECC, which combines HED with V-LDPC, is proposed. In XEE ECC, HED detects errors and error correction capability of LDPC ECC is enhanced. Moreover, V-LDPC averages the number of detected errors among encode/decode unit and error correction capability further improves. As a result, the data-retention lifetime is increased by 230% and the acceptable BER is increased by 90% in 3D NAND flash.
Keyword (in Japanese) (See Japanese page) 
(in English) 3D-TLC NAND flash memories / error detection / LDPC ECC / SSD / / / /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 10, ICD2018-1, pp. 1-6, April 2018.
Paper # ICD2018-1 
Date of Issue 2018-04-12 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ICD  
Conference Date 2018-04-19 - 2018-04-20 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2018-04-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Reliability Enhancement Technique with Horizontal Error Detection and Vertical-LDPC in 3D-TLC NAND Flash Memories 
Sub Title (in English)  
Keyword(1) 3D-TLC NAND flash memories  
Keyword(2) error detection  
Keyword(3) LDPC ECC  
Keyword(4) SSD  
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1st Author's Name Shun Suzuki  
1st Author's Affiliation Chuo University (Chuo Univ.)
2nd Author's Name Yoshiaki Deguchi  
2nd Author's Affiliation Chuo University (Chuo Univ.)
3rd Author's Name Toshiki Nakamura  
3rd Author's Affiliation Chuo University (Chuo Univ.)
4th Author's Name Kyoji Mizoguchi  
4th Author's Affiliation Chuo University (Chuo Univ.)
5th Author's Name Ken Takeuchi  
5th Author's Affiliation Chuo University (Chuo Univ.)
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Speaker Author-1 
Date Time 2018-04-19 10:10:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2018-1 
Volume (vol) vol.118 
Number (no) no.10 
Page pp.1-6 
#Pages 6 
Date of Issue 2018-04-12 (ICD) 

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