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Paper Abstract and Keywords
Presentation 2018-04-20 09:55
[Invited Lecture] A new core transistor equipped with NVM functionality without using any emerging memory materials
Yasuhiro Taniguchi, Shoji Yoshida, Owada Fukuo, Yutaka Shinagawa, Hideo Kasai (Floadia), Lin Jia You, Wei I Huan (PTC), Daisuke Okada, Koichi Nagasawa, Kosuke Okuyama (Floadia) ICD2018-7
Abstract (in Japanese) (See Japanese page) 
(in English) A tri-gate core transistor which has nonvolatile memory [NVM] functionality in midsection of a logic transistor gate was developed on 90nm CMOS process and demonstrated its functionality and validity. It is possible to be embedded into logic blocks seamlessly. Program and Erase [P/E] operation of the nonvolatile core transistor [NV Core Trs] is performed with ultra-low current by employing FN tunneling, and it is controlled by the circuits configured only with logic devices. No high voltage transistor is necessary in the logic blocks, and the area of peripheral circuits become extremely small. Integration of memory and logic becomes quite easy, and thus, some of new architecture and applications are possible to create without using any emerging memory materials. Proposed examples are ultra-high speed nonvolatile RAM [NVRAM] with direct conjunction of NV Core Trs and SRAM cell, and highly sophisticated secure NVM.
Keyword (in Japanese) (See Japanese page) 
(in English) nonvolatile / memory / NVRAM / NVSRAM / core / SONOS / scalability /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 10, ICD2018-7, pp. 23-27, April 2018.
Paper # ICD2018-7 
Date of Issue 2018-04-12 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ICD  
Conference Date 2018-04-19 - 2018-04-20 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2018-04-ICD 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A new core transistor equipped with NVM functionality without using any emerging memory materials 
Sub Title (in English)  
Keyword(1) nonvolatile  
Keyword(2) memory  
Keyword(3) NVRAM  
Keyword(4) NVSRAM  
Keyword(5) core  
Keyword(6) SONOS  
Keyword(7) scalability  
Keyword(8)  
1st Author's Name Yasuhiro Taniguchi  
1st Author's Affiliation Floadia Corporation (Floadia)
2nd Author's Name Shoji Yoshida  
2nd Author's Affiliation Floadia Corporation (Floadia)
3rd Author's Name Owada Fukuo  
3rd Author's Affiliation Floadia Corporation (Floadia)
4th Author's Name Yutaka Shinagawa  
4th Author's Affiliation Floadia Corporation (Floadia)
5th Author's Name Hideo Kasai  
5th Author's Affiliation Floadia Corporation (Floadia)
6th Author's Name Lin Jia You  
6th Author's Affiliation Powerchip Technology Corporation (PTC)
7th Author's Name Wei I Huan  
7th Author's Affiliation Powerchip Technology Corporation (PTC)
8th Author's Name Daisuke Okada  
8th Author's Affiliation Floadia Corporation (Floadia)
9th Author's Name Koichi Nagasawa  
9th Author's Affiliation Floadia Corporation (Floadia)
10th Author's Name Kosuke Okuyama  
10th Author's Affiliation Floadia Corporation (Floadia)
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Speaker Author-1 
Date Time 2018-04-20 09:55:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2018-7 
Volume (vol) vol.118 
Number (no) no.10 
Page pp.23-27 
#Pages 5 
Date of Issue 2018-04-12 (ICD) 

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