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Paper Abstract and Keywords
Presentation 2018-05-16 15:00
Non-volatile Power Gating for Data Cache with Dynamic Line-selection
Sosuke Akiba, Kimiyoshi Usami (SIT) VLD2018-2
Abstract (in Japanese) (See Japanese page) 
(in English) In the whole of CPU, the proportion of energy consumption of the cache is increasing. Non-volatile Power Gating(NVPG) is a technique of reducing the leakage power of the cache while keeping the stored data by applying the nonvolatile element MTJ to the SRAM that is constituting the cache. However, when PG is applied to data cache with Write-back writing system, there is a problem that information to be written in the main memory is lost and cache coherency cannot be maintained. In this paper, we examine the NVPG method applicable to the data cache that selects storage line based on decay miss density. Moreover, we evaluate the reduction of leakage power by the proposed method.
Keyword (in Japanese) (See Japanese page) 
(in English) Power-Gating / MTJ / data cache / Cache decay / / / /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 29, VLD2018-2, pp. 19-24, May 2018.
Paper # VLD2018-2 
Date of Issue 2018-05-09 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2018-2

Conference Information
Committee VLD IPSJ-SLDM  
Conference Date 2018-05-16 - 2018-05-16 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Design, etc. 
Paper Information
Registration To VLD 
Conference Code 2018-05-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Non-volatile Power Gating for Data Cache with Dynamic Line-selection 
Sub Title (in English)  
Keyword(1) Power-Gating  
Keyword(2) MTJ  
Keyword(3) data cache  
Keyword(4) Cache decay  
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1st Author's Name Sosuke Akiba  
1st Author's Affiliation Shibaura Institute of Technology (SIT)
2nd Author's Name Kimiyoshi Usami  
2nd Author's Affiliation Shibaura Institute of Technology (SIT)
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Speaker Author-1 
Date Time 2018-05-16 15:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2018-2 
Volume (vol) vol.118 
Number (no) no.29 
Page pp.19-24 
#Pages 6 
Date of Issue 2018-05-09 (VLD) 

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