Paper Abstract and Keywords |
Presentation |
2018-07-18 15:50
Case Study on a Verification of an IoT Architecture Model Based on Control Loop Yoshitaka Aoki (NUL), Shinpei Ogata, Kazuki Kobayashi (Shinshu Univ.), Hiroyuki Nakagawa (Osaka Univ.) SS2018-11 KBSE2018-21 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
IoT (Internet of Things) systems have their respective complicated configuration across cyber and physical space. Even if each component works normally, design faults of the interaction among those components may lead to accidents. However, no verification method for detecting such faults enough has been established. Many control loops, which are cyclic relations among IoT system components on their interactions, exist in IoT systems. A key to ensuring the safety of an IoT system is ensuring the stability of its control loops. In this paper, we propose a method to verify an IoT architecture model using a model checking technique focusing on the behaviors on the control loops represented in the model. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
IoT / Architecture / Model Checking / Control Loop / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 118, no. 138, KBSE2018-21, pp. 61-66, July 2018. |
Paper # |
KBSE2018-21 |
Date of Issue |
2018-07-11 (SS, KBSE) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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SS2018-11 KBSE2018-21 |
Conference Information |
Committee |
KBSE SS IPSJ-SE |
Conference Date |
2018-07-18 - 2018-07-20 |
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(See Japanese page) |
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Paper Information |
Registration To |
KBSE |
Conference Code |
2018-07-KBSE-SS-SE |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Case Study on a Verification of an IoT Architecture Model Based on Control Loop |
Sub Title (in English) |
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Keyword(1) |
IoT |
Keyword(2) |
Architecture |
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Model Checking |
Keyword(4) |
Control Loop |
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1st Author's Name |
Yoshitaka Aoki |
1st Author's Affiliation |
Nihon Unisys, Ltd. (NUL) |
2nd Author's Name |
Shinpei Ogata |
2nd Author's Affiliation |
Shinshu University (Shinshu Univ.) |
3rd Author's Name |
Kazuki Kobayashi |
3rd Author's Affiliation |
Shinshu University (Shinshu Univ.) |
4th Author's Name |
Hiroyuki Nakagawa |
4th Author's Affiliation |
Osaka University (Osaka Univ.) |
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Speaker |
Author-1 |
Date Time |
2018-07-18 15:50:00 |
Presentation Time |
25 minutes |
Registration for |
KBSE |
Paper # |
SS2018-11, KBSE2018-21 |
Volume (vol) |
vol.118 |
Number (no) |
no.137(SS), no.138(KBSE) |
Page |
pp.61-66 |
#Pages |
6 |
Date of Issue |
2018-07-11 (SS, KBSE) |
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