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Paper Abstract and Keywords
Presentation 2018-10-11 11:15
Area reduction of logic circuits using asymmetry AQFP gates and their demonstration
Yukihiro Okuma, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama Natl. Univ.) SCE2018-24
Abstract (in Japanese) (See Japanese page) 
(in English) Adiabatic quantum-flux-parametron (AQFP) circuits are expected as future energy-efficient high-performance information processing systems. In this study, we designed low-area logic circuits using asymmetry AQFP gates. We obtained a reasonably wide bias margin in the low-speed function tests. We also designed 4-to-16 decoder using asymmetry AQFP gates. Compared with one using conventional logic gates, we reduced the area of the circuit by 32% and the number of joseph junctions by 18% and confirmed the correct operation.
Keyword (in Japanese) (See Japanese page) 
(in English) superconducting integration circuits / adiabatic quantum-flux-parametron / AQFP / adiabatic logic / decoder / / /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 233, SCE2018-24, pp. 41-45, Oct. 2018.
Paper # SCE2018-24 
Date of Issue 2018-10-03 (SCE) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SCE2018-24

Conference Information
Committee SCE  
Conference Date 2018-10-10 - 2018-10-11 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SCE 
Conference Code 2018-10-SCE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Area reduction of logic circuits using asymmetry AQFP gates and their demonstration 
Sub Title (in English)  
Keyword(1) superconducting integration circuits  
Keyword(2) adiabatic quantum-flux-parametron  
Keyword(3) AQFP  
Keyword(4) adiabatic logic  
Keyword(5) decoder  
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1st Author's Name Yukihiro Okuma  
1st Author's Affiliation Yokohama National University (Yokohama Natl. Univ.)
2nd Author's Name Yuki Yamanashi  
2nd Author's Affiliation Yokohama National University (Yokohama Natl. Univ.)
3rd Author's Name Nobuyuki Yoshikawa  
3rd Author's Affiliation Yokohama National University (Yokohama Natl. Univ.)
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Speaker Author-1 
Date Time 2018-10-11 11:15:00 
Presentation Time 25 minutes 
Registration for SCE 
Paper # SCE2018-24 
Volume (vol) vol.118 
Number (no) no.233 
Page pp.41-45 
#Pages 5 
Date of Issue 2018-10-03 (SCE) 

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