Paper Abstract and Keywords |
Presentation |
2018-10-18 10:40
Research on Acceleration of DPDK Application by Utilizing FPGA Ikuo Otani, Fumihiko Sawazaki, Noritaka Horikome (NTT) NS2018-106 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We are researching on acceleration of SPP (Soft Patch Panel), which is high-speed DPDK software connecting VMs with physical NICs or other VMs. As a means of acceleration, application of FPGA is focused on.
In this paper, architecture and performance examination result of FPGA applied SPP are stated. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
SPP / DPDK / FPGA / Load Balancer / Scale Out / Virtual Machine / / |
Reference Info. |
IEICE Tech. Rep., vol. 118, no. 250, NS2018-106, pp. 7-12, Oct. 2018. |
Paper # |
NS2018-106 |
Date of Issue |
2018-10-11 (NS) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
NS2018-106 |
Conference Information |
Committee |
NS |
Conference Date |
2018-10-18 - 2018-10-19 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kyoto Kyoiku Bunka Center |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Network architecture (Overlay, P2P, Ubiquitous network, Scale-free network, Active network, NGN, New Generation Network), Next generation packet transport (High speed Ethernet, IP over WDM, Multi-service package technology, MPLS), Grid, etc. |
Paper Information |
Registration To |
NS |
Conference Code |
2018-10-NS |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Research on Acceleration of DPDK Application by Utilizing FPGA |
Sub Title (in English) |
|
Keyword(1) |
SPP |
Keyword(2) |
DPDK |
Keyword(3) |
FPGA |
Keyword(4) |
Load Balancer |
Keyword(5) |
Scale Out |
Keyword(6) |
Virtual Machine |
Keyword(7) |
|
Keyword(8) |
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1st Author's Name |
Ikuo Otani |
1st Author's Affiliation |
Nippon Telegraph and Telephone Corporation (NTT) |
2nd Author's Name |
Fumihiko Sawazaki |
2nd Author's Affiliation |
Nippon Telegraph and Telephone Corporation (NTT) |
3rd Author's Name |
Noritaka Horikome |
3rd Author's Affiliation |
Nippon Telegraph and Telephone Corporation (NTT) |
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Speaker |
Author-1 |
Date Time |
2018-10-18 10:40:00 |
Presentation Time |
25 minutes |
Registration for |
NS |
Paper # |
NS2018-106 |
Volume (vol) |
vol.118 |
Number (no) |
no.250 |
Page |
pp.7-12 |
#Pages |
6 |
Date of Issue |
2018-10-11 (NS) |
|