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Paper Abstract and Keywords
Presentation 2018-12-06 10:55
A Tiny Memory implementation on an FPGA using Feature-Map Separable Convolution Technique
Akira Jinguji, Simpei Sato, Hiroki Nakahara (titech) RECONF2018-41
Abstract (in Japanese) (See Japanese page) 
(in English) Object detection and image recognition using a convolutional neural network (CNN) are used in embedded systems. Embedded systems require reasonable price and power performance. CNN has high accuracy and large computation. In realizing CNN, real-time processing cannot be realized in CPUs, and power consumption is too large in GPUs. The CNN realization of the FPGA is low power consumption, but large on-chip memory are required. Large memory FPGAs are expensive. Feature-map size output in convolution layers is large. This is a bottleneck in FPGA memory resource restrictions. We propose Feature-Map Separable Convolution. This makes an inference with divided feature-map. The feature-map size becomes smaller when an input image size becomes smaller. Thus, the buffer memory can be reduced. By experiments, we accomplished that the accuracy of CNN does not change so much with making buffer memory to 70%.
Keyword (in Japanese) (See Japanese page) 
(in English) Deep learning / CNN / FPGA / / / / /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 340, RECONF2018-41, pp. 39-44, Dec. 2018.
Paper # RECONF2018-41 
Date of Issue 2018-11-28 (RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2018-41

Conference Information
Committee VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM 
Conference Date 2018-12-05 - 2018-12-07 
Place (in Japanese) (See Japanese page) 
Place (in English) Satellite Campus Hiroshima 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2018 -New Field of VLSI Design- 
Paper Information
Registration To RECONF 
Conference Code 2018-12-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Tiny Memory implementation on an FPGA using Feature-Map Separable Convolution Technique 
Sub Title (in English)  
Keyword(1) Deep learning  
Keyword(2) CNN  
Keyword(3) FPGA  
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1st Author's Name Akira Jinguji  
1st Author's Affiliation Tokyo Institute of Technology (titech)
2nd Author's Name Simpei Sato  
2nd Author's Affiliation Tokyo Institute of Technology (titech)
3rd Author's Name Hiroki Nakahara  
3rd Author's Affiliation Tokyo Institute of Technology (titech)
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Speaker Author-1 
Date Time 2018-12-06 10:55:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2018-41 
Volume (vol) vol.118 
Number (no) no.340 
Page pp.39-44 
#Pages 6 
Date of Issue 2018-11-28 (RECONF) 

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