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Paper Abstract and Keywords
Presentation 2018-12-07 14:35
An Efficient Multiplier Employing Time-Encoded Stochastic Computing Circuit
Tati Erlina, Renyuan Zhang, Yasuhiko Nakashima (NAIST) CPSY2018-41
Abstract (in Japanese) (See Japanese page) 
(in English) A compact multiplier circuit is designed by time-encoded stochastic computing technology. The operands of multiplication are represented by the cycle duty of pulse signals. Using the Neuron-MOS technology, an efficiently tunable pulse-generator is proposed without digital pulse-width-modulation (PWM). The multiplication of two time-encoded stochastic numbers is obtained through a simple logic gate. The proof-of-concept multiplier is designed in a 0.18um CMOS technology. The total amount of MOS transistors is reduced to 3% of the traditional time-encoded stochastic calculator. From the circuit simulation results, the calculation accuracy of 85% is achieved; and the energy for one single operation is slightly reduced from the existing works with 5 x speed.
Keyword (in Japanese) (See Japanese page) 
(in English) Approximate Computing / Time-encoded Stochastic / Neuron-MOS / / / / /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 339, CPSY2018-41, pp. 47-52, Dec. 2018.
Paper # CPSY2018-41 
Date of Issue 2018-11-28 (CPSY) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2018-41

Conference Information
Committee VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM 
Conference Date 2018-12-05 - 2018-12-07 
Place (in Japanese) (See Japanese page) 
Place (in English) Satellite Campus Hiroshima 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2018 -New Field of VLSI Design- 
Paper Information
Registration To CPSY 
Conference Code 2018-12-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Efficient Multiplier Employing Time-Encoded Stochastic Computing Circuit 
Sub Title (in English)  
Keyword(1) Approximate Computing  
Keyword(2) Time-encoded Stochastic  
Keyword(3) Neuron-MOS  
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1st Author's Name Tati Erlina  
1st Author's Affiliation Nara Institute of Science and Technology (NAIST)
2nd Author's Name Renyuan Zhang  
2nd Author's Affiliation Nara Institute of Science and Technology (NAIST)
3rd Author's Name Yasuhiko Nakashima  
3rd Author's Affiliation Nara Institute of Science and Technology (NAIST)
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Speaker Author-1 
Date Time 2018-12-07 14:35:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2018-41 
Volume (vol) vol.118 
Number (no) no.339 
Page pp.47-52 
#Pages 6 
Date of Issue 2018-11-28 (CPSY) 

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