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Paper Abstract and Keywords
Presentation 2019-01-30 15:05
Design and implementation of FPGA measurement feedback system in Coherent Ising Machine
Toshimori Honjo, Takahiro Inagaki, Kensuke Inaba, Takuya Ikuta, Hiroki Takesue (NTT) VLD2018-78 CPSY2018-88 RECONF2018-52
Abstract (in Japanese) (See Japanese page) 
(in English) To solve combinatorial optimization problems, the way to utilize new type of computer that can find ground state of Ising model has been getting attention. Coherent Ising machine is one of such analog computers, that utilizes a network of degenerated optical paramteric oscillators in an optical cavity for solving ground-state-search problems. The interaction between optical pulses is realized by measurment and feedback scheme, which performend in every circulation in the optical cavity. This measurment-and-feedback system requires both real-time processing and large matrix multipuication, thus it is suitable for FPGA application. In this paper, we describe our prototype implementation of a FPGA measurment-and-feedback system.
Keyword (in Japanese) (See Japanese page) 
(in English) Coherent Ising Machine / Ising model / measruemnt and feedback / FPGA / / / /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 432, RECONF2018-52, pp. 37-42, Jan. 2019.
Paper # RECONF2018-52 
Date of Issue 2019-01-23 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2018-78 CPSY2018-88 RECONF2018-52

Conference Information
Committee IPSJ-SLDM RECONF VLD CPSY IPSJ-ARC  
Conference Date 2019-01-30 - 2019-01-31 
Place (in Japanese) (See Japanese page) 
Place (in English) Raiosha, Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To RECONF 
Conference Code 2019-01-SLDM-RECONF-VLD-CPSY-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design and implementation of FPGA measurement feedback system in Coherent Ising Machine 
Sub Title (in English)  
Keyword(1) Coherent Ising Machine  
Keyword(2) Ising model  
Keyword(3) measruemnt and feedback  
Keyword(4) FPGA  
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1st Author's Name Toshimori Honjo  
1st Author's Affiliation Nippon Telegraph and Telephone Corporation (NTT)
2nd Author's Name Takahiro Inagaki  
2nd Author's Affiliation Nippon Telegraph and Telephone Corporation (NTT)
3rd Author's Name Kensuke Inaba  
3rd Author's Affiliation Nippon Telegraph and Telephone Corporation (NTT)
4th Author's Name Takuya Ikuta  
4th Author's Affiliation Nippon Telegraph and Telephone Corporation (NTT)
5th Author's Name Hiroki Takesue  
5th Author's Affiliation Nippon Telegraph and Telephone Corporation (NTT)
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Speaker Author-1 
Date Time 2019-01-30 15:05:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2018-78, CPSY2018-88, RECONF2018-52 
Volume (vol) vol.118 
Number (no) no.430(VLD), no.431(CPSY), no.432(RECONF) 
Page pp.37-42 
#Pages 6 
Date of Issue 2019-01-23 (VLD, CPSY, RECONF) 

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