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| Presentation | 2019-02-27 11:45 An Efficient Approach to Recycled FPGA Detection Using WID Variation Modeling Foisal Ahmed, Michihiro Shintani, Michiko Inoue (NAIST)  DC2018-77 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Recycled field programmable gate arrays (FPGAs) make a significant threat to mission critical systems due to their performance degradation and shorter lifetime caused by aging. In this paper, we propose a novel recycled FPGA detection method based on with-in die (WID) variation modeling. While fresh/recycled classification is carried out using measured frequencies from ring oscillators on FPGA in existing methods, the proposed method exploits model parameters extracted from the WID modeling. The model parameters simply and accurately represent the process variation of each FPGA, and thus the classification performs very well by the simple feature vector. Experimental results using circuit simulation demonstrate that the proposed method achieves 99.6% dimension reduction per FPGA chip with showing 96.0% detection accuracy using one-class support vector machine (SVM); while our silicon results on Xilinx Artix-7 FPGAs demonstrate the model parameters have good distance properties between fresh and aged. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Recycled detection / Field programmable gate array (FPGA) / Process variation / With-in die process variation / Feature engineering / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 118, no. 456, DC2018-77, pp. 37-42, Feb. 2019. | |
| Paper # | DC2018-77 | |
| Date of Issue | 2019-02-20 (DC) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | DC2018-77 |
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| Conference Information | |
| Committee | DC |
| Conference Date | 2019-02-27 - 2019-02-27 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Design and Test, etc. |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2019-02-DC |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Efficient Approach to Recycled FPGA Detection Using WID Variation Modeling |
| Sub Title (in English) | |
| Keyword(1) | Recycled detection |
| Keyword(2) | Field programmable gate array (FPGA) |
| Keyword(3) | Process variation |
| Keyword(4) | With-in die process variation |
| Keyword(5) | Feature engineering |
| Keyword(6) | |
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| Keyword(8) | |
| 1st Author's Name | Foisal Ahmed |
| 1st Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
| 2nd Author's Name | Michihiro Shintani |
| 2nd Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
| 3rd Author's Name | Michiko Inoue |
| 3rd Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
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| Speaker | Author-1 |
| Date Time | 2019-02-27 11:45:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | DC2018-77 |
| Volume (vol) | vol.118 |
| Number (no) | no.456 |
| Page | pp.37-42 |
| #Pages | 6 |
| Date of Issue | 2019-02-20 (DC) |
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