Paper Abstract and Keywords |
Presentation |
2019-04-18 11:10
FPGA prototype of autonomous Time Aware Shaper for low-latency layer 2 switch Kazuto Nishimura, Masaki Hirota, Takafumi Terahara, Hideki Matsui (Fujitsu) CS2019-5 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In 5th Generation mobile communication, it is considered that Mobile Front Haul (MFH) network is integrated to Layer 2 network because of network efficiency. However, in such a network, MFH traffic may be influenced by other traffic in point of delay. As MFH traffic is delay-sensitive, IEEE802.1-Time Sensitive Networking (TSN) is paid attention because it may achieve low latency communication in packet network. In this paper, we focus on IEEE802.1Qbv (Time Aware Shaper : TAS) which is one of the queueing architecture of TSN. We have proposed the autonomous TAS method called intelligent TAS (iTAS) which could solve the operational problem previously, and have verified the principle of iTAS by using software prototype. In this paper, we implement a part of iTAS function to FPGA and achieve 1000 times more granularity
improvement. This result shows that our method can be applied to actual MFH environment. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Low-latency / Layer 2 switch / IEEE802.1 TSN / IEEE802.1Qbv / iTAS / Mobile Front Haul / / |
Reference Info. |
IEICE Tech. Rep., vol. 119, no. 6, CS2019-5, pp. 25-30, April 2019. |
Paper # |
CS2019-5 |
Date of Issue |
2019-04-11 (CS) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CS2019-5 |
Conference Information |
Committee |
CS CQ |
Conference Date |
2019-04-18 - 2019-04-19 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Osaka Univ. Library |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Optical/Wireless Access and Their Integration, QoS and QoE, Assessment / Measurement / Control / Optimization of Communication Quality, Network Services, etc |
Paper Information |
Registration To |
CS |
Conference Code |
2019-04-CS-CQ |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
FPGA prototype of autonomous Time Aware Shaper for low-latency layer 2 switch |
Sub Title (in English) |
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Keyword(1) |
Low-latency |
Keyword(2) |
Layer 2 switch |
Keyword(3) |
IEEE802.1 TSN |
Keyword(4) |
IEEE802.1Qbv |
Keyword(5) |
iTAS |
Keyword(6) |
Mobile Front Haul |
Keyword(7) |
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Keyword(8) |
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1st Author's Name |
Kazuto Nishimura |
1st Author's Affiliation |
Fujitsu LTD (Fujitsu) |
2nd Author's Name |
Masaki Hirota |
2nd Author's Affiliation |
Fujitsu LTD (Fujitsu) |
3rd Author's Name |
Takafumi Terahara |
3rd Author's Affiliation |
Fujitsu LTD (Fujitsu) |
4th Author's Name |
Hideki Matsui |
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Fujitsu LTD (Fujitsu) |
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Speaker |
Author-1 |
Date Time |
2019-04-18 11:10:00 |
Presentation Time |
25 minutes |
Registration for |
CS |
Paper # |
CS2019-5 |
Volume (vol) |
vol.119 |
Number (no) |
no.6 |
Page |
pp.25-30 |
#Pages |
6 |
Date of Issue |
2019-04-11 (CS) |
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