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Paper Abstract and Keywords
Presentation 2019-04-19 09:55
Demonstration of an SFQ/CMOS hybrid memory system using a one-instruction-set SFQ microprocessor
Yuki Hironaka, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.) SCE2019-2
Abstract (in Japanese) (See Japanese page) 
(in English) SFQ/CMOS hybrid system, which is a hybridized system of SFQ circuits and CMOS memories, has been proposed as a large-scale memory solution for single-flux-quantum (SFQ) circuits. In this study, we designed and tested an SFQ microprocessor with an SFQ/CMOS hybrid memory, which we had implemented so far, for the demonstration of the SFQ/CMOS hybrid system. We adopted a one-instruction-set-computer architecture, SUBNEG. The system was designed and implemented with superconducting interface circuits by using the Josephson integrated circuit process, AIST-ADP2. A 64-kb SFQ/CMOS hybrid memory was combined with the SFQ microprocessor, where SFQ processor can access to a 16×4-bit memory space. In the measurement, the correct operation between the SFQ processor and the CMOS memory was obtained, and a simple integer sorting program was demonstrated.
Keyword (in Japanese) (See Japanese page) 
(in English) SFQ/CMOS hybrid system / Josephson/CMOS hybrid memory / SFQ circuits / SRAM / one-instruction-set computer / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 10, SCE2019-2, pp. 7-11, April 2019.
Paper # SCE2019-2 
Date of Issue 2019-04-12 (SCE) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee SCE  
Conference Date 2019-04-19 - 2019-04-19 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SCE 
Conference Code 2019-04-SCE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Demonstration of an SFQ/CMOS hybrid memory system using a one-instruction-set SFQ microprocessor 
Sub Title (in English)  
Keyword(1) SFQ/CMOS hybrid system  
Keyword(2) Josephson/CMOS hybrid memory  
Keyword(3) SFQ circuits  
Keyword(4) SRAM  
Keyword(5) one-instruction-set computer  
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1st Author's Name Yuki Hironaka  
1st Author's Affiliation Yokohama National University (Yokohama National Univ.)
2nd Author's Name Yuki Yamanashi  
2nd Author's Affiliation Yokohama National University (Yokohama National Univ.)
3rd Author's Name Nobuyuki Yoshikawa  
3rd Author's Affiliation Yokohama National University (Yokohama National Univ.)
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Speaker Author-1 
Date Time 2019-04-19 09:55:00 
Presentation Time 25 minutes 
Registration for SCE 
Paper # SCE2019-2 
Volume (vol) vol.119 
Number (no) no.10 
Page pp.7-11 
#Pages 5 
Date of Issue 2019-04-12 (SCE) 

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