Paper Abstract and Keywords |
Presentation |
2019-07-23 13:35
Side-channel leakage evaluation of cryptographic module by IC chip level consumption simulation Kazuki Yasuda, Kazuki Monta, Akihiro Tsukioka, Noriyuki Miura, Makoto Nagata (Kobe Univ.) ISEC2019-27 SITE2019-21 BioX2019-19 HWS2019-22 ICSS2019-25 EMM2019-30 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
With the development of the information society, side-channel information leakage due to power supply noise in a cryptographic module using semiconductor integrated circuit (IC chip) technology has become an issue. In this research, we propose a method to make chip level simulation efficient by using a transistor device model for power consumption current of a cryptographic engine mounted on an IC chip. The chip to be evaluated is equipped with the Advanced Encryption Standard (AES) encryption. There are two target files. One is a netlist in which logic operation called RTL is described from combination of transfer between register and logic operation and logic synthesis is performed, and the other is netlist in which placement and routing are performed using logic synthesized netlist. We operated simulation during cryptographic and obtained the waveform of the wire consumption current. We operate CPA using the acquired waveform data, and power supply noise evaluation was performed. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
IC chip / Power Noise / Crypto Modules / Side-channel leakage / AES / simulation / / |
Reference Info. |
IEICE Tech. Rep., vol. 119, no. 143, HWS2019-22, pp. 139-143, July 2019. |
Paper # |
HWS2019-22 |
Date of Issue |
2019-07-16 (ISEC, SITE, BioX, HWS, ICSS, EMM) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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ISEC2019-27 SITE2019-21 BioX2019-19 HWS2019-22 ICSS2019-25 EMM2019-30 |
Conference Information |
Committee |
ISEC SITE ICSS EMM HWS BioX IPSJ-CSEC IPSJ-SPT |
Conference Date |
2019-07-23 - 2019-07-24 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kochi University of Technology |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Security, etc. |
Paper Information |
Registration To |
HWS |
Conference Code |
2019-07-ISEC-SITE-ICSS-EMM-HWS-BioX-CSEC-SPT |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Side-channel leakage evaluation of cryptographic module by IC chip level consumption simulation |
Sub Title (in English) |
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Keyword(1) |
IC chip |
Keyword(2) |
Power Noise |
Keyword(3) |
Crypto Modules |
Keyword(4) |
Side-channel leakage |
Keyword(5) |
AES |
Keyword(6) |
simulation |
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1st Author's Name |
Kazuki Yasuda |
1st Author's Affiliation |
Kobe University (Kobe Univ.) |
2nd Author's Name |
Kazuki Monta |
2nd Author's Affiliation |
Kobe University (Kobe Univ.) |
3rd Author's Name |
Akihiro Tsukioka |
3rd Author's Affiliation |
Kobe University (Kobe Univ.) |
4th Author's Name |
Noriyuki Miura |
4th Author's Affiliation |
Kobe University (Kobe Univ.) |
5th Author's Name |
Makoto Nagata |
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Kobe University (Kobe Univ.) |
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Speaker |
Author-1 |
Date Time |
2019-07-23 13:35:00 |
Presentation Time |
25 minutes |
Registration for |
HWS |
Paper # |
ISEC2019-27, SITE2019-21, BioX2019-19, HWS2019-22, ICSS2019-25, EMM2019-30 |
Volume (vol) |
vol.119 |
Number (no) |
no.140(ISEC), no.141(SITE), no.142(BioX), no.143(HWS), no.144(ICSS), no.145(EMM) |
Page |
pp.139-143 |
#Pages |
5 |
Date of Issue |
2019-07-16 (ISEC, SITE, BioX, HWS, ICSS, EMM) |
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