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Paper Abstract and Keywords
Presentation 2019-07-24 13:45
Design Space Search Applying Bayesian Optimization to High-level Design Flow
Ryohei Nakayama (UTokyo), Hiromitsu Awano (Osaka Univ.), Makoto Ikeda (UTokyo) ISEC2019-57 SITE2019-51 BioX2019-49 HWS2019-52 ICSS2019-55 EMM2019-60
Abstract (in Japanese) (See Japanese page) 
(in English) Now that circuit scale is increasing, high-level synthesis technology that designs circuits using high-level programming languages with high abstraction levels, rather than hardware design languages with low abstraction levels, is drawing attention.
On the other hand, it is important to search the design space efficiently in order to determine the design parameters such as the operating frequency and loop constraints required for high-level synthesis.
In this presentation, we propose a method to find the optimal solution while avoiding local solutions by using Bayesian optimization for design parameter search.
Keyword (in Japanese) (See Japanese page) 
(in English) High-Level Synthesis / Bayesian Optimization / Design Space Search / Montgomery Multiplication / Residue Number System / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 143, HWS2019-52, pp. 369-374, July 2019.
Paper # HWS2019-52 
Date of Issue 2019-07-16 (ISEC, SITE, BioX, HWS, ICSS, EMM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ISEC2019-57 SITE2019-51 BioX2019-49 HWS2019-52 ICSS2019-55 EMM2019-60

Conference Information
Committee ISEC SITE ICSS EMM HWS BioX IPSJ-CSEC IPSJ-SPT 
Conference Date 2019-07-23 - 2019-07-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Kochi University of Technology 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Security, etc. 
Paper Information
Registration To HWS 
Conference Code 2019-07-ISEC-SITE-ICSS-EMM-HWS-BioX-CSEC-SPT 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design Space Search Applying Bayesian Optimization to High-level Design Flow 
Sub Title (in English)  
Keyword(1) High-Level Synthesis  
Keyword(2) Bayesian Optimization  
Keyword(3) Design Space Search  
Keyword(4) Montgomery Multiplication  
Keyword(5) Residue Number System  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Ryohei Nakayama  
1st Author's Affiliation The University of Tokyo (UTokyo)
2nd Author's Name Hiromitsu Awano  
2nd Author's Affiliation Osaka University (Osaka Univ.)
3rd Author's Name Makoto Ikeda  
3rd Author's Affiliation The University of Tokyo (UTokyo)
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Speaker Author-1 
Date Time 2019-07-24 13:45:00 
Presentation Time 25 minutes 
Registration for HWS 
Paper # ISEC2019-57, SITE2019-51, BioX2019-49, HWS2019-52, ICSS2019-55, EMM2019-60 
Volume (vol) vol.119 
Number (no) no.140(ISEC), no.141(SITE), no.142(BioX), no.143(HWS), no.144(ICSS), no.145(EMM) 
Page pp.369-374 
#Pages 6 
Date of Issue 2019-07-16 (ISEC, SITE, BioX, HWS, ICSS, EMM) 

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