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Paper Abstract and Keywords
Presentation 2019-11-01 16:00
A Study of Hardware Trojan Detection Method using Deep Learning in Asynchronous Circuits
Hikaru Inafune, Masashi Imai (Hirosaki Univ.) HWS2019-63 ICD2019-24
Abstract (in Japanese) (See Japanese page) 
(in English) There are typically two timing methods in VLSI designs known as
synchronous circuits which use a global clock and asynchronous circuits which are based on the request-and-acknowledge handshaking protocols. In this paper, we show the effectiveness of using the appropriate feature values for asynchronous circuits in order to detect asynchronous hardware Trojans based on the deep learning methods at the netlist design phase. We show that the deep learning method to detect synchronous hardware Trojan nets is also effective to detect asynchronous hardware Trojan nets by using asynchronous hardware Trojan circuits at the training phase. We also show that the appropriate feature values to detect asynchronous hardware Trojans have a great potential to increase the performance of the classifiers.
Keyword (in Japanese) (See Japanese page) 
(in English) Asynchronous Circuits / Hardware Trojan / Deep Learning / Hardware Trojan Detection Method / / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 260, HWS2019-63, pp. 35-40, Nov. 2019.
Paper # HWS2019-63 
Date of Issue 2019-10-25 (HWS, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF HWS2019-63 ICD2019-24

Conference Information
Committee HWS ICD  
Conference Date 2019-11-01 - 2019-11-01 
Place (in Japanese) (See Japanese page) 
Place (in English) DNP Namba SS Bld. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Hardware Security, etc. 
Paper Information
Registration To HWS 
Conference Code 2019-11-HWS-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Study of Hardware Trojan Detection Method using Deep Learning in Asynchronous Circuits 
Sub Title (in English)  
Keyword(1) Asynchronous Circuits  
Keyword(2) Hardware Trojan  
Keyword(3) Deep Learning  
Keyword(4) Hardware Trojan Detection Method  
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Keyword(6)  
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1st Author's Name Hikaru Inafune  
1st Author's Affiliation Hirosaki University (Hirosaki Univ.)
2nd Author's Name Masashi Imai  
2nd Author's Affiliation Hirosaki University (Hirosaki Univ.)
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Speaker Author-2 
Date Time 2019-11-01 16:00:00 
Presentation Time 25 minutes 
Registration for HWS 
Paper # HWS2019-63, ICD2019-24 
Volume (vol) vol.119 
Number (no) no.260(HWS), no.261(ICD) 
Page pp.35-40 
#Pages 6 
Date of Issue 2019-10-25 (HWS, ICD) 

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