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Paper Abstract and Keywords
Presentation 2019-11-14 14:40
Ferroelectric FET-based Parallel Product-Sum Operation Neuromorphic Circuits
Koki Kamimura, Susumu Nohmi, Ken Takeuchi (Chuo Univ.) ICD2019-31 IE2019-37
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, Moore’s Law which has supported the improvement of semiconductor performance is coming to an end. Therefore, neuromorphic computing has attracted attention instead of conventional von Neumann computing. Among neuromorphic computing, neuromorphic circuits using non-volatile memory have particularly attracted attention. However, conventional neuromorphic circuits are small range of weight and high power consumption. This paper proposes neuromorphic circuits using ferroelectric-FET (FeFET). FeFET is a kind of non-volatile memory and has feature that the dynamic range of cell current is wide. Therefore, the range of weight is also wide. In addition, proposed neuromorphic circuits achieve low power consumption and a number of product-sum operations in parallel.
Keyword (in Japanese) (See Japanese page) 
(in English) FeFET / Neuromorphic / Dynamic range of cell current / Parallel product-sum operation / / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 284, ICD2019-31, pp. 13-17, Nov. 2019.
Paper # ICD2019-31 
Date of Issue 2019-11-06 (ICD, IE) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2019-31 IE2019-37

Conference Information
Committee VLD DC CPSY RECONF ICD IE IPSJ-SLDM IPSJ-EMB 
Conference Date 2019-11-13 - 2019-11-15 
Place (in Japanese) (See Japanese page) 
Place (in English) Ehime Prefecture Gender Equality Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2019 -New Field of VLSI Design- 
Paper Information
Registration To ICD 
Conference Code 2019-11-VLD-DC-CPSY-RECONF-ICD-IE-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Ferroelectric FET-based Parallel Product-Sum Operation Neuromorphic Circuits 
Sub Title (in English)  
Keyword(1) FeFET  
Keyword(2) Neuromorphic  
Keyword(3) Dynamic range of cell current  
Keyword(4) Parallel product-sum operation  
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1st Author's Name Koki Kamimura  
1st Author's Affiliation Chuo University (Chuo Univ.)
2nd Author's Name Susumu Nohmi  
2nd Author's Affiliation Chuo University (Chuo Univ.)
3rd Author's Name Ken Takeuchi  
3rd Author's Affiliation Chuo University (Chuo Univ.)
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Speaker Author-1 
Date Time 2019-11-14 14:40:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2019-31, IE2019-37 
Volume (vol) vol.119 
Number (no) no.284(ICD), no.285(IE) 
Page pp.13-17 
#Pages 5 
Date of Issue 2019-11-06 (ICD, IE) 

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