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Paper Abstract and Keywords
Presentation 2019-11-14 16:10
Analysis of Fault Detection Degradation Issue in Multi-cycle Test Scheme using Probabilistic Evaluation Method
Norihiro Nakaoka, Tomoki Aono, Sohshi Kudoh, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas) VLD2019-45 DC2019-69
Abstract (in Japanese) (See Japanese page) 
(in English) In order to ensure the functional safety of advanced autonomous driving systems, a power-on self-test
(POST) is required to diagnose the presence or absence of a device fault by using a logical built-in self-test (LBIST)
mechanism at system startup. We must obtain a fault detection rate defined under strict test execution time
constraints. Multi-cycle testing is one of the effective methods for shortening POST execution time using LBIST.
However, in the multi-cycle test, there was a fault detection degradation problem that made it difficult for the
capture pattern to detect a new stuck-at fault as the number of capture cycles increased. Regarding the cause of
the fault detection degradation problem, it has been found that many flip-flops (FF) values become fixed as the
number of cycles increases in multi-cycle tests by performing logic / fault simulations. The relationship between
such a problem and fault detection has not yet been clarified. In this paper, we analyze the mechanism of the
fault detection degradation problem by evaluating the transition probability and fault detection probability of the
capture pattern sequence in the multi-cycle test scheme using a probability-based testability evaluation scale called
COP.
Keyword (in Japanese) (See Japanese page) 
(in English) POST / LBIST / Multi-cycle Testing / Function Safety / Stuck-at Fault / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 283, DC2019-69, pp. 145-150, Nov. 2019.
Paper # DC2019-69 
Date of Issue 2019-11-06 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2019-45 DC2019-69

Conference Information
Committee VLD DC CPSY RECONF ICD IE IPSJ-SLDM IPSJ-EMB 
Conference Date 2019-11-13 - 2019-11-15 
Place (in Japanese) (See Japanese page) 
Place (in English) Ehime Prefecture Gender Equality Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2019 -New Field of VLSI Design- 
Paper Information
Registration To DC 
Conference Code 2019-11-VLD-DC-CPSY-RECONF-ICD-IE-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Analysis of Fault Detection Degradation Issue in Multi-cycle Test Scheme using Probabilistic Evaluation Method 
Sub Title (in English)  
Keyword(1) POST  
Keyword(2) LBIST  
Keyword(3) Multi-cycle Testing  
Keyword(4) Function Safety  
Keyword(5) Stuck-at Fault  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Norihiro Nakaoka  
1st Author's Affiliation Ehime University (Ehime Univ.)
2nd Author's Name Tomoki Aono  
2nd Author's Affiliation Ehime University (Ehime Univ.)
3rd Author's Name Sohshi Kudoh  
3rd Author's Affiliation Ehime University (Ehime Univ.)
4th Author's Name Senling Wang  
4th Author's Affiliation Ehime University (Ehime Univ.)
5th Author's Name Yoshinobu Higami  
5th Author's Affiliation Ehime University (Ehime Univ.)
6th Author's Name Hiroshi Takahashi  
6th Author's Affiliation Ehime University (Ehime Univ.)
7th Author's Name Hiroyuki Iwata  
7th Author's Affiliation Renesas Electronics Corporation (Renesas)
8th Author's Name Yoichi Maeda  
8th Author's Affiliation Renesas Electronics Corporation (Renesas)
9th Author's Name Jun Matsushima  
9th Author's Affiliation Renesas Electronics Corporation (Renesas)
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Speaker Author-3 
Date Time 2019-11-14 16:10:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # VLD2019-45, DC2019-69 
Volume (vol) vol.119 
Number (no) no.282(VLD), no.283(DC) 
Page pp.145-150 
#Pages 6 
Date of Issue 2019-11-06 (VLD, DC) 

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