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| Presentation | 2019-11-14 09:40 FPGA implementation of ISA-based sparse CNN using Wide-SIMD Akira Jinguji, Shimpei Sato, Hiroki Nakahara (Titech)  RECONF2019-37 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Convolutional Neural Network (CNN) achieves high recognition performance in image recognition, and is expected to be applied in embedded systems such as automobiles and security cameras. Embedded systems are required to be realized with inexpensive devices and to have excellent power performance. In image recognition, CNN achieves a discrimination accuracy much higher than that of existing methods, but the CPU cannot realize real-time processing and the GPU consumes too much power. Computational power is inferior to GPU. There is weight sparseness as a method for speeding up CNN. In weighted sparse CNN, most of the parameters are zero, and the product-sum operation including zero accounts for the majority. In order to calculate the weighted sparse CNN at high speed, it is necessary to skip the multiply-add operation including zero, but to skip zero calculation, random access to the memory is required. Random access is generally slower than sequential access. In particular, because GPUs have slow random access, zero skipping is a bottleneck in CNN calculations. In this paper, we propose an FPGA implementation method of CNN calculation that efficiently performs zero skipping using Wide-SIMD. We think that CNN inference can be performed at high speed by using a SIMD-type arithmetic array and on-chip memory as a wide-band buffer. The circuit was designed using Xilinx Vivado HLS and implemented on Digilent PYNQ-Z1. As a result of the experiment, a speed of 86 image/s was achieved with VGG-based YOLOv2. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | CNN / FPGA / / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 119, no. 287, RECONF2019-37, pp. 9-14, Nov. 2019. | |
| Paper # | RECONF2019-37 | |
| Date of Issue | 2019-11-07 (RECONF) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2019-37 |
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| Conference Information | |
| Committee | VLD DC CPSY RECONF ICD IE IPSJ-SLDM IPSJ-EMB |
| Conference Date | 2019-11-13 - 2019-11-15 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ehime Prefecture Gender Equality Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2019 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2019-11-VLD-DC-CPSY-RECONF-ICD-IE-SLDM-EMB-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | FPGA implementation of ISA-based sparse CNN using Wide-SIMD |
| Sub Title (in English) | |
| Keyword(1) | CNN |
| Keyword(2) | FPGA |
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| 1st Author's Name | Akira Jinguji |
| 1st Author's Affiliation | Tokyo Institute of Technology (Titech) |
| 2nd Author's Name | Shimpei Sato |
| 2nd Author's Affiliation | Tokyo Institute of Technology (Titech) |
| 3rd Author's Name | Hiroki Nakahara |
| 3rd Author's Affiliation | Tokyo Institute of Technology (Titech) |
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| Speaker | Author-1 |
| Date Time | 2019-11-14 09:40:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2019-37 |
| Volume (vol) | vol.119 |
| Number (no) | no.287 |
| Page | pp.9-14 |
| #Pages | 6 |
| Date of Issue | 2019-11-07 (RECONF) |
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