Paper Abstract and Keywords |
Presentation |
2019-12-23 16:20
InP Wafer-level Backside Process for Future Tera-hertz Operation Takuya Tsutsumi, Hiroshi Hamada, Hiroki Sugiyama, Hideyuki Nosaka, Hideaki Matsuzaki (NTT) ED2019-82 Link to ES Tech. Rep. Archives: ED2019-82 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The sub-millimeter-wave band would be utilized in future mobile networks to cope with increasing data rates. InP-based SMMIC (Submillimeter-wave monolithic ICs) have attracted much attention because InP-based transistors feature superior RF characteristics. This paper reports wafer-level backside process technology consists of thinning a 3-inch InP wafer, forming dense vias, backside metalization with single-level wiring. We also applied the developed backside bias-lines to an actual SMMIC in order to enhance IC layout effectiveness and reduce electric loss of the RF signals. Finally, we successfully demonstrate a power amplifier with the world’s highest level output power of +9.5 dBm up to the 300-GHz range without any degradation of transistor characteristics. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
SubmiIIimeter-wave monolithic ICs (SMMICs) / Indium phosphide (InP) / (InP),Wafer-level backside process / backside lines / High electron mobility transistors (HEMTs) / Heterojunction bipolar transistors (HBTs) / / |
Reference Info. |
IEICE Tech. Rep., vol. 119, no. 353, ED2019-82, pp. 23-28, Dec. 2019. |
Paper # |
ED2019-82 |
Date of Issue |
2019-12-16 (ED) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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ED2019-82 Link to ES Tech. Rep. Archives: ED2019-82 |