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Presentation 2020-01-17 13:15
[Poster Presentation] Study of low power consumption of adiabatic pass transistor decoder for Josephson-CMOS Hybrid Memories
Yu Okamoto, Yuki Hironaka, Nobuyuki Yoshikawa (Yokohama Natl. Univ.) SCE2019-49 Link to ES Tech. Rep. Archives: SCE2019-49
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, superconducting circuits have attracted attention because of the limitation of CMOS circuit technology. However, it is challenging to construct a large-scale memory by only using the superconducting circuit. To overcome this, a Josephson-CMOS hybrid memory using CMOS memory cells has been proposed [1].
In this study, we reduced the energy consumption of the Josephson-CMOS hybrid memory by using an adiabatic CMOS circuit using transmission gates. The adiabatic CMOS concept is adopted in a decoder design, where its energy consumption occupies about 30% of that of the Josephson-CMOS hybrid memory. We investigated the relationship between a phase number of power supplies and the energy efficiency in 8-bit adiabatic CMOS decoders by circuit simulations. We found that a single-phase power supply method is the most efficient in terms of hardware cost and energy efficiency.
Keyword (in Japanese) (See Japanese page) 
(in English) Josephson-CMOS hybrid memory / adiabatic CMOS circuit / transmission gates / phase number of power supplies / / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 369, SCE2019-49, pp. 79-81, Jan. 2020.
Paper # SCE2019-49 
Date of Issue 2020-01-09 (SCE) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SCE2019-49 Link to ES Tech. Rep. Archives: SCE2019-49

Conference Information
Committee SCE  
Conference Date 2020-01-16 - 2020-01-17 
Place (in Japanese) (See Japanese page) 
Place (in English)  
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Paper Information
Registration To SCE 
Conference Code 2020-01-SCE 
Language English (Japanese title is available) 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Study of low power consumption of adiabatic pass transistor decoder for Josephson-CMOS Hybrid Memories 
Sub Title (in English)  
Keyword(1) Josephson-CMOS hybrid memory  
Keyword(2) adiabatic CMOS circuit  
Keyword(3) transmission gates  
Keyword(4) phase number of power supplies  
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1st Author's Name Yu Okamoto  
1st Author's Affiliation Yokohama National University (Yokohama Natl. Univ.)
2nd Author's Name Yuki Hironaka  
2nd Author's Affiliation Yokohama National University (Yokohama Natl. Univ.)
3rd Author's Name Nobuyuki Yoshikawa  
3rd Author's Affiliation Yokohama National University (Yokohama Natl. Univ.)
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Speaker Author-1 
Date Time 2020-01-17 13:15:00 
Presentation Time 135 minutes 
Registration for SCE 
Paper # SCE2019-49 
Volume (vol) vol.119 
Number (no) no.369 
Page pp.79-81 
#Pages
Date of Issue 2020-01-09 (SCE) 


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