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Paper Abstract and Keywords
Presentation 2020-01-23 14:45
Study of a Simplified Digital Spiking Neuron and Its FPGA Implementation
Tomohiro Yoneda (NII) VLD2019-75 CPSY2019-73 RECONF2019-65
Abstract (in Japanese) (See Japanese page) 
(in English) A simplified digital spiking neural network implementable on FPGAs is proposed in order to reduce necessary resources and power consumption. An idea to improve a GA (Genetic Algorithm)-based learning algorithm is also discussed. Several comparison results with a low precision ANN (Artificial Neural Network) are shown.
Keyword (in Japanese) (See Japanese page) 
(in English) Spiking neural networks / Digital spiking neurons / GA(Genetic Algorithm) / FPGA implementation / / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 373, RECONF2019-65, pp. 135-140, Jan. 2020.
Paper # RECONF2019-65 
Date of Issue 2020-01-15 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2019-75 CPSY2019-73 RECONF2019-65

Conference Information
Committee IPSJ-SLDM RECONF VLD CPSY IPSJ-ARC  
Conference Date 2020-01-22 - 2020-01-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Raiosha, Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To RECONF 
Conference Code 2020-01-SLDM-RECONF-VLD-CPSY-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Study of a Simplified Digital Spiking Neuron and Its FPGA Implementation 
Sub Title (in English)  
Keyword(1) Spiking neural networks  
Keyword(2) Digital spiking neurons  
Keyword(3) GA(Genetic Algorithm)  
Keyword(4) FPGA implementation  
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1st Author's Name Tomohiro Yoneda  
1st Author's Affiliation National Institute of Informatics (NII)
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Speaker Author-1 
Date Time 2020-01-23 14:45:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2019-75, CPSY2019-73, RECONF2019-65 
Volume (vol) vol.119 
Number (no) no.371(VLD), no.372(CPSY), no.373(RECONF) 
Page pp.135-140 
#Pages 6 
Date of Issue 2020-01-15 (VLD, CPSY, RECONF) 

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