Paper Abstract and Keywords |
Presentation |
2020-03-11 12:10
A Construction Method of Garbled Circuits for ZDD Takayuki Masui, Hikaru Morita (Graduate Schoool, Kanagawa Univ) IT2019-114 ISEC2019-110 WBS2019-63 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Kruger et al proposed a new method to construct Garbled Circuits for BDD, which gives a compression expression of logic function. The method has compressed memory and it is secure under semi-honest assumption. In this paper, the authors propose a construction method of Garbled Circuits for ZDD which improves the method for BDD and consider the memory compression effect of the proposed method. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
secure computation / Garbled Circuit / ZDD / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 119, no. 474, ISEC2019-110, pp. 167-170, March 2020. |
Paper # |
ISEC2019-110 |
Date of Issue |
2020-03-03 (IT, ISEC, WBS) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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IT2019-114 ISEC2019-110 WBS2019-63 |
Conference Information |
Committee |
ISEC IT WBS |
Conference Date |
2020-03-10 - 2020-03-11 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
University of Hyogo |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
joint meeting of IT, ISEC, and WBS |
Paper Information |
Registration To |
ISEC |
Conference Code |
2020-03-ISEC-IT-WBS |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Construction Method of Garbled Circuits for ZDD |
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secure computation |
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Garbled Circuit |
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ZDD |
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1st Author's Name |
Takayuki Masui |
1st Author's Affiliation |
Graduate School of Engineering, Kanagawa University (Graduate Schoool, Kanagawa Univ) |
2nd Author's Name |
Hikaru Morita |
2nd Author's Affiliation |
Graduate School of Engineering, Kanagawa University (Graduate Schoool, Kanagawa Univ) |
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Speaker |
Author-1 |
Date Time |
2020-03-11 12:10:00 |
Presentation Time |
25 minutes |
Registration for |
ISEC |
Paper # |
IT2019-114, ISEC2019-110, WBS2019-63 |
Volume (vol) |
vol.119 |
Number (no) |
no.473(IT), no.474(ISEC), no.475(WBS) |
Page |
pp.167-170 |
#Pages |
4 |
Date of Issue |
2020-03-03 (IT, ISEC, WBS) |
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