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Paper Abstract and Keywords
Presentation 2020-07-30 11:00
Instruction Prefetcher focusing on properties of Prefetch Distance
Tomoki Nakamura, Toru Koizumi, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya (UTokyo) CPSY2020-1 DC2020-1
Abstract (in Japanese) (See Japanese page) 
(in English) Instruction cache misses and branch target buffer (BTB) misses are performance bottlenecks in recent applications,
and many instruction prefetchers have been proposed to eliminate them. In order for these prefetchers to work effectively, it is
important to issue prefetch at a sufficiently early timing using a long prefetch distance. In addition, we found that increasing
the prefetch distance improves not only the prefetch timing but also the coverage. Therefore, we propose a D-JOLT prefetcher
that takes advantage of a large prefetch distance. D-JOLT is a prefetcher that learns and prediction by signatures using the
information of function calls. D-JOLT achieves highly accurate prediction of a distant future with a hybrid configuration of
prefetchers with different prediction accuracy and a signature that uses the number of consecutive return instructions. We
evaluated D-JOLT with traces distributed in The First Instruction Prefetching Championship, and D-JOLT achieves a 52.0%
performance improvement over a processor without an instruction prefetching and a 21.5% performance improvement over the
state of the art prefetcher.
Keyword (in Japanese) (See Japanese page) 
(in English) prefetching / instruction cache / branch target buffer / / / / /  
Reference Info. IEICE Tech. Rep., vol. 120, no. 121, CPSY2020-1, pp. 1-8, July 2020.
Paper # CPSY2020-1 
Date of Issue 2020-07-23 (CPSY, DC) 
ISSN Online edition: ISSN 2432-6380
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2020-1 DC2020-1

Conference Information
Committee CPSY DC IPSJ-ARC  
Conference Date 2020-07-30 - 2020-07-31 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) SWoPP2020: Parallel, Distributed and Cooperative Processing Systems and Dependable Computing 
Paper Information
Registration To CPSY 
Conference Code 2020-07-CPSY-DC-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Instruction Prefetcher focusing on properties of Prefetch Distance 
Sub Title (in English)  
Keyword(1) prefetching  
Keyword(2) instruction cache  
Keyword(3) branch target buffer  
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1st Author's Name Tomoki Nakamura  
1st Author's Affiliation The University of Tokyo (UTokyo)
2nd Author's Name Toru Koizumi  
2nd Author's Affiliation The University of Tokyo (UTokyo)
3rd Author's Name Yuya Degawa  
3rd Author's Affiliation The University of Tokyo (UTokyo)
4th Author's Name Hidetsugu Irie  
4th Author's Affiliation The University of Tokyo (UTokyo)
5th Author's Name Shuichi Sakai  
5th Author's Affiliation The University of Tokyo (UTokyo)
6th Author's Name Ryota Shioya  
6th Author's Affiliation The University of Tokyo (UTokyo)
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Speaker Author-1 
Date Time 2020-07-30 11:00:00 
Presentation Time 30 minutes 
Registration for CPSY 
Paper # CPSY2020-1, DC2020-1 
Volume (vol) vol.120 
Number (no) no.121(CPSY), no.122(DC) 
Page pp.1-8 
#Pages
Date of Issue 2020-07-23 (CPSY, DC) 


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