Paper Abstract and Keywords |
Presentation |
2020-08-07 11:25
Gate-all-around p-type poly-Si junctionless nanowire transistor with steep subthreshold slope Min-Ju Ahn, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto (IIS, Tokyo Univ.) SDM2020-9 ICD2020-9 Link to ES Tech. Rep. Archives: SDM2020-9 ICD2020-9 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this work, GAA p-type junctionless nanowire transistor with BF2+ implanted poly-Si channel have been fabricated and evaluated. It exhibits excellent subthreshold slope (SS) close to ideal SS value as well as high on/off current ratio and low off-current. It is mainly attributted to that fluorine ions introduced during BF2+ implantation can produce high quaility of poly-Si channel by effectively passivating grain boundary defects, and segregation of boron ions during high temperature channel thinning process, which results in larger grain size (reduced grain boundary defects) and reduced channel concentration. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Gate-all-around / Junctionless / Poly-Si / Fluorine passivation / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 120, no. 126, SDM2020-9, pp. 41-46, Aug. 2020. |
Paper # |
SDM2020-9 |
Date of Issue |
2020-07-30 (SDM, ICD) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
SDM2020-9 ICD2020-9 Link to ES Tech. Rep. Archives: SDM2020-9 ICD2020-9 |
Conference Information |
Committee |
ICD SDM ITE-IST |
Conference Date |
2020-08-06 - 2020-08-07 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Online |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications |
Paper Information |
Registration To |
SDM |
Conference Code |
2020-08-ICD-SDM-IST |
Language |
English |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Gate-all-around p-type poly-Si junctionless nanowire transistor with steep subthreshold slope |
Sub Title (in English) |
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Keyword(1) |
Gate-all-around |
Keyword(2) |
Junctionless |
Keyword(3) |
Poly-Si |
Keyword(4) |
Fluorine passivation |
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1st Author's Name |
Min-Ju Ahn |
1st Author's Affiliation |
Institute of Industrial Science, The University of Tokyo (IIS, Tokyo Univ.) |
2nd Author's Name |
Takuya Saraya |
2nd Author's Affiliation |
Institute of Industrial Science, The University of Tokyo (IIS, Tokyo Univ.) |
3rd Author's Name |
Masaharu Kobayashi |
3rd Author's Affiliation |
Institute of Industrial Science, The University of Tokyo (IIS, Tokyo Univ.) |
4th Author's Name |
Toshiro Hiramoto |
4th Author's Affiliation |
Institute of Industrial Science, The University of Tokyo (IIS, Tokyo Univ.) |
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Speaker |
Author-1 |
Date Time |
2020-08-07 11:25:00 |
Presentation Time |
25 minutes |
Registration for |
SDM |
Paper # |
SDM2020-9, ICD2020-9 |
Volume (vol) |
vol.120 |
Number (no) |
no.126(SDM), no.127(ICD) |
Page |
pp.41-46 |
#Pages |
6 |
Date of Issue |
2020-07-30 (SDM, ICD) |
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