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Paper Abstract and Keywords
Presentation 2020-11-17 14:25
Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder
Naoto Soga, Shimpei Sato, HIroki Nakahara (Tokyo Tech) VLD2020-17 ICD2020-37 DC2020-37 RECONF2020-36
Abstract (in Japanese) (See Japanese page) 
(in English) Advancements in portable electrocardiographs have allowed electrocardiogram (ECG) signals to be recorded in everyday life. Machine-learning techniques, including deep learning, have been used in numerous studies to analyze ECG signals because they exhibit superior performance to conventional methods. However, deep-learning based models often have too many parameters to implement on mobile hardware, its amount of hardware is too large and dissipates much power consumption. We propose a design flow to implement the outlier detector using an autoencoder on a low-end FPGA. To shorten the preparation time of ECG data used in training an autoencoder, an unsupervised learning technique is applied. Additionally, to minimize the volume of the weight parameters, a weight sparseness technique is applied. Also, all the parameters are converted into fixed-point values, and weight sharing technique was applied to further reduce the weight parameter volume. We implemented the autoencoder on a Digilent Inc. ZedBoard and compared the results with those for the ARM mobile CPU for a built-in device. The results indicated that our FPGA implementation of the outlier detector was 12 times faster and 106 times more energy-efficient.
Keyword (in Japanese) (See Japanese page) 
(in English) outlier detection / autoencoder / unsupervised learning / FPGA / / / /  
Reference Info. IEICE Tech. Rep., vol. 120, no. 237, RECONF2020-36, pp. 36-41, Nov. 2020.
Paper # RECONF2020-36 
Date of Issue 2020-11-10 (VLD, ICD, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2020-17 ICD2020-37 DC2020-37 RECONF2020-36

Conference Information
Committee VLD DC RECONF ICD IPSJ-SLDM  
Conference Date 2020-11-17 - 2020-11-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2020 -New Field of VLSI Design- 
Paper Information
Registration To RECONF 
Conference Code 2020-11-VLD-DC-RECONF-ICD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder 
Sub Title (in English)  
Keyword(1) outlier detection  
Keyword(2) autoencoder  
Keyword(3) unsupervised learning  
Keyword(4) FPGA  
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1st Author's Name Naoto Soga  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
2nd Author's Name Shimpei Sato  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
3rd Author's Name HIroki Nakahara  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
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Speaker Author-1 
Date Time 2020-11-17 14:25:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2020-17, ICD2020-37, DC2020-37, RECONF2020-36 
Volume (vol) vol.120 
Number (no) no.234(VLD), no.235(ICD), no.236(DC), no.237(RECONF) 
Page pp.36-41 
#Pages 6 
Date of Issue 2020-11-10 (VLD, ICD, DC, RECONF) 

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