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Paper Abstract and Keywords
Presentation 2020-11-17 10:30
Power Analysis Based on Probability Calculation of Small Regions in LSI
Ryo Oba, Ryu Hoshino, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) VLD2020-13 ICD2020-33 DC2020-33 RECONF2020-32 Link to ES Tech. Rep. Archives: ICD2020-33
Abstract (in Japanese) (See Japanese page) 
(in English) Power consumption in LSI testing is higher than in functional mode since more switching activities occur. High power consumption causes excessive IR-drop and excessive delay, resulting in test malfunction. Excessive IR-drop does not uniformly occur in the whole area of circuit, but in certain areas where many switching activities occur. Therefore, it is important for efficient reduction of excessive IR-drop to locate areas where many switching activities occur during LSI testing. In this work, we propose a method to locate areas where many switching activities occur by focusing on the probability calculation for the combination of several logic gates in LSI design data.
Keyword (in Japanese) (See Japanese page) 
(in English) at-speed testing / test power / IR-drop / transition delay test / test malfunction / probability of switching activity / /  
Reference Info. IEICE Tech. Rep., vol. 120, no. 236, DC2020-33, pp. 12-17, Nov. 2020.
Paper # DC2020-33 
Date of Issue 2020-11-10 (VLD, ICD, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2020-13 ICD2020-33 DC2020-33 RECONF2020-32 Link to ES Tech. Rep. Archives: ICD2020-33

Conference Information
Committee VLD DC RECONF ICD IPSJ-SLDM  
Conference Date 2020-11-17 - 2020-11-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2020 -New Field of VLSI Design- 
Paper Information
Registration To DC 
Conference Code 2020-11-VLD-DC-RECONF-ICD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Power Analysis Based on Probability Calculation of Small Regions in LSI 
Sub Title (in English)  
Keyword(1) at-speed testing  
Keyword(2) test power  
Keyword(3) IR-drop  
Keyword(4) transition delay test  
Keyword(5) test malfunction  
Keyword(6) probability of switching activity  
Keyword(7)  
Keyword(8)  
1st Author's Name Ryo Oba  
1st Author's Affiliation Kyushu Institute of Technology (Kyutech)
2nd Author's Name Ryu Hoshino  
2nd Author's Affiliation Kyushu Institute of Technology (Kyutech)
3rd Author's Name Kohei Miyase  
3rd Author's Affiliation Kyushu Institute of Technology (Kyutech)
4th Author's Name Xiaoqing Wen  
4th Author's Affiliation Kyushu Institute of Technology (Kyutech)
5th Author's Name Seiji Kajihara  
5th Author's Affiliation Kyushu Institute of Technology (Kyutech)
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Speaker Author-1 
Date Time 2020-11-17 10:30:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # VLD2020-13, ICD2020-33, DC2020-33, RECONF2020-32 
Volume (vol) vol.120 
Number (no) no.234(VLD), no.235(ICD), no.236(DC), no.237(RECONF) 
Page pp.12-17 
#Pages
Date of Issue 2020-11-10 (VLD, ICD, DC, RECONF) 


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