Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2020-11-17 10:30
Power Analysis Based on Probability Calculation of Small Regions in LSI
Ryo Oba, Ryu Hoshino, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) VLD2020-13 ICD2020-33 DC2020-33 RECONF2020-32
Abstract (in Japanese) (See Japanese page) 
(in English) Power consumption in LSI testing is higher than in functional mode since more switching activities occur. High power consumption causes excessive IR-drop and excessive delay, resulting in test malfunction. Excessive IR-drop does not uniformly occur in the whole area of circuit, but in certain areas where many switching activities occur. Therefore, it is important for efficient reduction of excessive IR-drop to locate areas where many switching activities occur during LSI testing. In this work, we propose a method to locate areas where many switching activities occur by focusing on the probability calculation for the combination of several logic gates in LSI design data.
Keyword (in Japanese) (See Japanese page) 
(in English) at-speed testing / test power / IR-drop / transition delay test / test malfunction / probability of switching activity / /  
Reference Info. IEICE Tech. Rep., vol. 120, no. 236, DC2020-33, pp. 12-17, Nov. 2020.
Paper # DC2020-33 
Date of Issue 2020-11-10 (VLD, ICD, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2020-13 ICD2020-33 DC2020-33 RECONF2020-32

Conference Information
Committee VLD DC RECONF ICD IPSJ-SLDM  
Conference Date 2020-11-17 - 2020-11-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2020 -New Field of VLSI Design- 
Paper Information
Registration To DC 
Conference Code 2020-11-VLD-DC-RECONF-ICD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Power Analysis Based on Probability Calculation of Small Regions in LSI 
Sub Title (in English)  
Keyword(1) at-speed testing  
Keyword(2) test power  
Keyword(3) IR-drop  
Keyword(4) transition delay test  
Keyword(5) test malfunction  
Keyword(6) probability of switching activity  
Keyword(7)  
Keyword(8)  
1st Author's Name Ryo Oba  
1st Author's Affiliation Kyushu Institute of Technology (Kyutech)
2nd Author's Name Ryu Hoshino  
2nd Author's Affiliation Kyushu Institute of Technology (Kyutech)
3rd Author's Name Kohei Miyase  
3rd Author's Affiliation Kyushu Institute of Technology (Kyutech)
4th Author's Name Xiaoqing Wen  
4th Author's Affiliation Kyushu Institute of Technology (Kyutech)
5th Author's Name Seiji Kajihara  
5th Author's Affiliation Kyushu Institute of Technology (Kyutech)
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2020-11-17 10:30:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # VLD2020-13, ICD2020-33, DC2020-33, RECONF2020-32 
Volume (vol) vol.120 
Number (no) no.234(VLD), no.235(ICD), no.236(DC), no.237(RECONF) 
Page pp.12-17 
#Pages 6 
Date of Issue 2020-11-10 (VLD, ICD, DC, RECONF) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan