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Paper Abstract and Keywords
Presentation 2021-01-26 12:45
SLM based FPGA-IP soft core
Yuya Nakazato, Hiroaki Koga (Kumamoto Univ.), Zhao Qian (KIT), Motoki Amagasaki, Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) VLD2020-61 CPSY2020-44 RECONF2020-80
Abstract (in Japanese) (See Japanese page) 
(in English) In the recent edge computing infrastructure, MEC (Multi-access Edge Computing) devices is considered to reduce the load on IoT devices by offloading the processing at the edge terminals, and to ensure real-time performance between servers and edges. MEC requires dynamic response to the number of connected terminals and computing processes, as well as small size, high speed, and low power consumption. In this paper, we propose an implementation of SLM (Scalable Logic Module) based FPGA-IP with reasonable performance efficiency and a manufacturing test method by developing a design tool. In this study, we explored the SLM based FPGA architecture and proposed a test method for 1, 0 stack at faults. The evaluation results show that the proposed method can achieve a smaller area than the LUT-based FPGA-IP and can detect 100% of degenerate faults in the proposed FPGA-IP.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Soft IP(Soft Macro) / Logic Cell / Shipping Test / / / /  
Reference Info. IEICE Tech. Rep., vol. 120, no. 339, RECONF2020-80, pp. 125-130, Jan. 2021.
Paper # RECONF2020-80 
Date of Issue 2021-01-18 (VLD, CPSY, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2020-61 CPSY2020-44 RECONF2020-80

Conference Information
Committee CPSY RECONF VLD IPSJ-ARC IPSJ-SLDM  
Conference Date 2021-01-25 - 2021-01-26 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To RECONF 
Conference Code 2021-01-CPSY-RECONF-VLD-ARC-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) SLM based FPGA-IP soft core 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Soft IP(Soft Macro)  
Keyword(3) Logic Cell  
Keyword(4) Shipping Test  
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Keyword(6)  
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1st Author's Name Yuya Nakazato  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Hiroaki Koga  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ.)
3rd Author's Name Zhao Qian  
3rd Author's Affiliation Kyushu Institute of Technology (KIT)
4th Author's Name Motoki Amagasaki  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
5th Author's Name Morihiro Kuga  
5th Author's Affiliation Kumamoto University (Kumamoto Univ.)
6th Author's Name Masahiro Iida  
6th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Speaker Author-1 
Date Time 2021-01-26 12:45:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2020-61, CPSY2020-44, RECONF2020-80 
Volume (vol) vol.120 
Number (no) no.337(VLD), no.338(CPSY), no.339(RECONF) 
Page pp.125-130 
#Pages 6 
Date of Issue 2021-01-18 (VLD, CPSY, RECONF) 

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