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| Presentation | 2021-03-01 17:30 Examination by simulation of high frequency gate driver using 0.5 μm CMOS/SOI Keisuke Otani, Minami Nakayama, Kazuma Ariyoshi, Satoshi Matsumoto (KIT)  EE2020-47 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In recent years, with the miniaturization and high performance of electronic devices and communication devices, miniaturization of power sources has been required. Increasing the switching frequency is effective as a miniaturization of the power supply. GaN power devices are highly efficient at high frequencies and are also excellent at high temperatures. In addition, thin-layer SOI is suitable for high-temperature operation because it can reduce leakage current and suppress latch-up. In this paper, we model a thin-layer SOI power MOFET and report the results of simulating a high-frequency gate driver for GaN power devices using SOI. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | GaN / gate driver / SOI / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 120, no. 387, EE2020-47, pp. 39-43, March 2021. | |
| Paper # | EE2020-47 | |
| Date of Issue | 2021-02-22 (EE) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | EE2020-47 |
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| Conference Information | |
| Committee | EE IEE-SPC |
| Conference Date | 2021-03-01 - 2021-03-02 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | EE |
| Conference Code | 2021-03-EE-SPC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Examination by simulation of high frequency gate driver using 0.5 μm CMOS/SOI |
| Sub Title (in English) | |
| Keyword(1) | GaN |
| Keyword(2) | gate driver |
| Keyword(3) | SOI |
| Keyword(4) | |
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| 1st Author's Name | Keisuke Otani |
| 1st Author's Affiliation | Kyusyu Institute of Technology (KIT) |
| 2nd Author's Name | Minami Nakayama |
| 2nd Author's Affiliation | Kyusyu Institute of Technology (KIT) |
| 3rd Author's Name | Kazuma Ariyoshi |
| 3rd Author's Affiliation | Kyusyu Institute of Technology (KIT) |
| 4th Author's Name | Satoshi Matsumoto |
| 4th Author's Affiliation | Kyusyu Institute of Technology (KIT) |
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| Speaker | Author-1 |
| Date Time | 2021-03-01 17:30:00 |
| Presentation Time | 20 minutes |
| Registration for | EE |
| Paper # | EE2020-47 |
| Volume (vol) | vol.120 |
| Number (no) | no.387 |
| Page | pp.39-43 |
| #Pages | 5 |
| Date of Issue | 2021-02-22 (EE) |
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