| IEICE Technical Committee Submission System Conference Paper's Information |
Online Proceedings [Sign in] Tech. Rep. Archives |
| Go Top Page | Go Previous | [Japanese] / [English] |
| Paper Abstract and Keywords | ||
| Presentation | 2021-03-04 13:50 Design and Evaluation of Efficient AES S-box Hardware with Optimization of Linear Mappings Ayano Nakashima, Rei Ueno, Naofumi Homma (Tohoku Univ.)  VLD2020-84 HWS2020-59 |
|
| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper presents a new AES S-Box hardware design based on the optimization of linear mappings by combining multiplicative and exponential offsets. In general, the performance of efficient AES S-Box hardware with composite field representations depends largely on the construction of linear mappings (i.e., transformation matrices) between AES polynomial field and the composite field before and after S-Box. Multiplicative and exponential offset techniques have been reported previously for obtaining the optimal transformation matrix, but the optimization combined with both techniques has been applied only to S-Box of Boyar-Peralta type variants. In this paper, we propose an application of multiplicative and exponential offsets to AES S-Box hardware based on redundant Galois field arithmetic. In particular, we design two types of the S-Box hardware: one for only encryption (ENC) and another for both encryption and decryption (ENC/DEC), and evaluate their performances by logic synthesis using Nangate 45nm Open Cell Library. From the evaluation applied area optimization constraints results, we show that the proposed S-Box hardware for ENC and ENC/DEC improves by 23.2% and 20.1% in the area delay product, respectively, compared with the conventional S-Box hardware based on redundant Galois field arithmetic. Moreover, we show that the proposed S-Box hardware for ENC and ENC/DEC is up to 8.7% and 28.8% better in area delay product, respectively, even compared with the most efficient ones. In the evaluation with frequency optimization constraints, we also show that proposed S-Box hardware for ENC and ENC/DEC achieve higher performance in comparison with the conventional ones. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | AES / S-Box / linear operations / ASIC / cryptographic hardware / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 120, no. 401, HWS2020-59, pp. 91-96, March 2021. | |
| Paper # | HWS2020-59 | |
| Date of Issue | 2021-02-24 (VLD, HWS) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2020-84 HWS2020-59 |
|
| Conference Information | |
| Committee | HWS VLD |
| Conference Date | 2021-03-03 - 2021-03-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Paper Information | |
| Registration To | HWS |
| Conference Code | 2021-03-HWS-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and Evaluation of Efficient AES S-box Hardware with Optimization of Linear Mappings |
| Sub Title (in English) | |
| Keyword(1) | AES |
| Keyword(2) | S-Box |
| Keyword(3) | linear operations |
| Keyword(4) | ASIC |
| Keyword(5) | cryptographic hardware |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Ayano Nakashima |
| 1st Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 2nd Author's Name | Rei Ueno |
| 2nd Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 3rd Author's Name | Naofumi Homma |
| 3rd Author's Affiliation | Tohoku University/CREST (Tohoku Univ.) |
| 4th Author's Name | |
| 4th Author's Affiliation | () |
| 5th Author's Name | |
| 5th Author's Affiliation | () |
| 6th Author's Name | |
| 6th Author's Affiliation | () |
| 7th Author's Name | |
| 7th Author's Affiliation | () |
| 8th Author's Name | |
| 8th Author's Affiliation | () |
| 9th Author's Name | |
| 9th Author's Affiliation | () |
| 10th Author's Name | |
| 10th Author's Affiliation | () |
| 11th Author's Name | |
| 11th Author's Affiliation | () |
| 12th Author's Name | |
| 12th Author's Affiliation | () |
| 13th Author's Name | |
| 13th Author's Affiliation | () |
| 14th Author's Name | |
| 14th Author's Affiliation | () |
| 15th Author's Name | |
| 15th Author's Affiliation | () |
| 16th Author's Name | |
| 16th Author's Affiliation | () |
| 17th Author's Name | |
| 17th Author's Affiliation | () |
| 18th Author's Name | |
| 18th Author's Affiliation | () |
| Speaker | Author-1 |
| Date Time | 2021-03-04 13:50:00 |
| Presentation Time | 25 minutes |
| Registration for | HWS |
| Paper # | VLD2020-84, HWS2020-59 |
| Volume (vol) | vol.120 |
| Number (no) | no.400(VLD), no.401(HWS) |
| Page | pp.91-96 |
| #Pages | 6 |
| Date of Issue | 2021-02-24 (VLD, HWS) |
[Return to Top Page]