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Paper Abstract and Keywords
Presentation 2021-03-04 09:30
Design space exploration on low energy embedded multi-core processors
Sayuri Onagi, Yuko Hara (Tokyo Tech) VLD2020-79 HWS2020-54
Abstract (in Japanese) (See Japanese page) 
(in English) Nowadays, edge computing has been sought by increasing stream data and demand for real time processing so that distributed computing can be enabled in real time on IoT edge devices that are placed on the user side. For architecture design towards edge computing, small circuit area, energy-saving, and design productivity are major concerns. This paper aims to develop design productivity of designing energy-efficient multicore processors that consist in tiny CPU cores of One Instruction Set Computers (OISCs). By building a performance and power estimation model in the early design stage, our work enables efficient design space exploration to determine the appropriate multicore structure for target applications.
Keyword (in Japanese) (See Japanese page) 
(in English) IoT / Multicore processor / Design space exploration / / / / /  
Reference Info. IEICE Tech. Rep., vol. 120, no. 400, VLD2020-79, pp. 61-66, March 2021.
Paper # VLD2020-79 
Date of Issue 2021-02-24 (VLD, HWS) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2020-79 HWS2020-54

Conference Information
Committee HWS VLD  
Conference Date 2021-03-03 - 2021-03-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon, Hardware Security, etc. 
Paper Information
Registration To VLD 
Conference Code 2021-03-HWS-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design space exploration on low energy embedded multi-core processors 
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Keyword(1) IoT  
Keyword(2) Multicore processor  
Keyword(3) Design space exploration  
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1st Author's Name Sayuri Onagi  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
2nd Author's Name Yuko Hara  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
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Speaker Author-1 
Date Time 2021-03-04 09:30:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2020-79, HWS2020-54 
Volume (vol) vol.120 
Number (no) no.400(VLD), no.401(HWS) 
Page pp.61-66 
#Pages 6 
Date of Issue 2021-02-24 (VLD, HWS) 

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