Paper Abstract and Keywords |
Presentation |
2021-10-28 16:20
Study on rounding error and Learning performance of reinforcement learning model for FPGA implementation Daisuke Oguchi, Satoshi Moriya, Hideaki Yamamoto, Shigeo Sato (Tohoku Univ) NC2021-24 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In recent years, the hardware implementation of reinforcement learning (RL) has attracted attention due to its wide range availability. We study a dedicated hardware architecture, which efficiently executes RL algorithm, and its realization in an FPGA. We investigated the learning performance when the bit-length was limited and found that the performance was maintained even when the bit-length was limited to 16, which results in saving circuit resources and power consumption. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Reinforcement Learning / FPGA / Q-learning / Edge Computing / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 121, no. 223, NC2021-24, pp. 34-39, Oct. 2021. |
Paper # |
NC2021-24 |
Date of Issue |
2021-10-21 (NC) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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NC2021-24 |
Conference Information |
Committee |
MBE NC |
Conference Date |
2021-10-28 - 2021-10-29 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Online |
Topics (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
NC |
Conference Code |
2021-10-MBE-NC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Study on rounding error and Learning performance of reinforcement learning model for FPGA implementation |
Sub Title (in English) |
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Keyword(1) |
Reinforcement Learning |
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FPGA |
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Q-learning |
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Edge Computing |
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1st Author's Name |
Daisuke Oguchi |
1st Author's Affiliation |
Tohoku University (Tohoku Univ) |
2nd Author's Name |
Satoshi Moriya |
2nd Author's Affiliation |
Tohoku University (Tohoku Univ) |
3rd Author's Name |
Hideaki Yamamoto |
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Tohoku University (Tohoku Univ) |
4th Author's Name |
Shigeo Sato |
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Tohoku University (Tohoku Univ) |
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Speaker |
Author-1 |
Date Time |
2021-10-28 16:20:00 |
Presentation Time |
25 minutes |
Registration for |
NC |
Paper # |
NC2021-24 |
Volume (vol) |
vol.121 |
Number (no) |
no.223 |
Page |
pp.34-39 |
#Pages |
6 |
Date of Issue |
2021-10-21 (NC) |
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