IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2021-10-28 16:20
Study on rounding error and Learning performance of reinforcement learning model for FPGA implementation
Daisuke Oguchi, Satoshi Moriya, Hideaki Yamamoto, Shigeo Sato (Tohoku Univ) NC2021-24
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, the hardware implementation of reinforcement learning (RL) has attracted attention due to its wide range availability. We study a dedicated hardware architecture, which efficiently executes RL algorithm, and its realization in an FPGA. We investigated the learning performance when the bit-length was limited and found that the performance was maintained even when the bit-length was limited to 16, which results in saving circuit resources and power consumption.
Keyword (in Japanese) (See Japanese page) 
(in English) Reinforcement Learning / FPGA / Q-learning / Edge Computing / / / /  
Reference Info. IEICE Tech. Rep., vol. 121, no. 223, NC2021-24, pp. 34-39, Oct. 2021.
Paper # NC2021-24 
Date of Issue 2021-10-21 (NC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF NC2021-24

Conference Information
Committee MBE NC  
Conference Date 2021-10-28 - 2021-10-29 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To NC 
Conference Code 2021-10-MBE-NC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Study on rounding error and Learning performance of reinforcement learning model for FPGA implementation 
Sub Title (in English)  
Keyword(1) Reinforcement Learning  
Keyword(2) FPGA  
Keyword(3) Q-learning  
Keyword(4) Edge Computing  
1st Author's Name Daisuke Oguchi  
1st Author's Affiliation Tohoku University (Tohoku Univ)
2nd Author's Name Satoshi Moriya  
2nd Author's Affiliation Tohoku University (Tohoku Univ)
3rd Author's Name Hideaki Yamamoto  
3rd Author's Affiliation Tohoku University (Tohoku Univ)
4th Author's Name Shigeo Sato  
4th Author's Affiliation Tohoku University (Tohoku Univ)
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2021-10-28 16:20:00 
Presentation Time 25 minutes 
Registration for NC 
Paper # NC2021-24 
Volume (vol) vol.121 
Number (no) no.223 
Page pp.34-39 
Date of Issue 2021-10-21 (NC) 

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan