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| Presentation | 2021-12-01 10:35 Basic evaluation of ReNA, a DNN accelerator using numerical representation posit Yasuhiro Nakahara, Yuta Masuda, Masato Kiyama, Motoki Amagasaki, Masahiro Iida (Kumamoto Univ.)  VLD2021-24 ICD2021-34 DC2021-30 RECONF2021-32 Link to ES Tech. Rep. Archives: ICD2021-34 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In Convolutional Neural Network (CNN) accelerators for edge, numerical precision of data should be reduced as much as possible to reduce the circuit area and the amount of data transfer. For this reason, Posit is attractive because it can achieve both low bit-width and high inference accuracy. In this paper, we present a basic evaluation of the inference accuracy and area of ReNA with Posit. In addition, Posit has a problem that its arithmetic unit is large compared to fixed-point circuit. In this paper, we describe a Float-like quire (FL quire) version arithmetic unit that we designed to solve this problem. A FL quire version arithmetic unit can optimize the circuit area according to CNN models. We also evaluated the implementation of this circuit in ReNA, and succeeded in reducing the area increase by about 1.2 times when optimized for ResNet-9. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Deep Learning / Convolutional Neural Network / AI chip / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 121, no. 280, RECONF2021-32, pp. 43-48, Dec. 2021. | |
| Paper # | RECONF2021-32 | |
| Date of Issue | 2021-11-24 (VLD, ICD, DC, RECONF) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2021-24 ICD2021-34 DC2021-30 RECONF2021-32 Link to ES Tech. Rep. Archives: ICD2021-34 |
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| Conference Information | |
| Committee | VLD DC RECONF ICD IPSJ-SLDM |
| Conference Date | 2021-12-01 - 2021-12-02 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2021 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2021-12-VLD-DC-RECONF-ICD-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Basic evaluation of ReNA, a DNN accelerator using numerical representation posit |
| Sub Title (in English) | |
| Keyword(1) | Deep Learning |
| Keyword(2) | Convolutional Neural Network |
| Keyword(3) | AI chip |
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| 1st Author's Name | Yasuhiro Nakahara |
| 1st Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 2nd Author's Name | Yuta Masuda |
| 2nd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 3rd Author's Name | Masato Kiyama |
| 3rd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 4th Author's Name | Motoki Amagasaki |
| 4th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 5th Author's Name | Masahiro Iida |
| 5th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
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| Speaker | Author-1 |
| Date Time | 2021-12-01 10:35:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | VLD2021-24, ICD2021-34, DC2021-30, RECONF2021-32 |
| Volume (vol) | vol.121 |
| Number (no) | no.277(VLD), no.278(ICD), no.279(DC), no.280(RECONF) |
| Page | pp.43-48 |
| #Pages | 6 |
| Date of Issue | 2021-11-24 (VLD, ICD, DC, RECONF) |
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