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| Presentation | 2021-12-01 09:20 Block Sparse MLP-based Vision DNN Accelerators on Embedded FPGAs Akira Jinguji, Hiroki Nakahara (Tokyo Tech)  VLD2021-21 ICD2021-31 DC2021-27 RECONF2021-29 Link to ES Tech. Rep. Archives: ICD2021-31 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Since the advent of Vision Transformer, a deep learning model for image recognition without Convolution, MLP-based models have attracted a lot of attention as an alternative to CNNs. MLP-based achieve high recognition accuracy in image recognition despite the lack of Convolution. Research on MLP-based, such as MLP-Mixer and gMLP, achieves high recognition accuracy with a simpler structure. For low-latency inference, the computational efficiency is reduced on GPUs due to the small amount of computational data per processing unit, and dedicated circuits such as FPGAs are considered to be more suitable. In this paper, we propose an FPGA circuit for an inference accelerator for MLP-based model, where we focus on efficiently computing the matrix product with high parallelism, since the simple matrix product in the MLP layer accounts for most of the computation in MLP-based models. We have designed a circuit that computes the product of two large matrices in one cycle by designing a bit-wide GEMM and a dedicated instruction set. In this paper, we implemented the proposed circuit on a Xilinx ZCU102 FPGA board and performed inference on the gMLP-S model. experimental results for class classification on the ImageNet dataset show that our implementation has a recognition accuracy of 74.5%, an inference speed of 159.0FPS and 6.3ms, and a power consumption of 24.9W. Compared to a mobile GPU, the proposed implementation is 4.4 times faster and 6.1 times more power efficient; compared to an existing FPGA implementation of the CNN model, our implementation has over 3% higher recognition accuracy with comparable inference speed. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | DNN / Vision Transformer / MLP / gMLP / FPGA / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 121, no. 280, RECONF2021-29, pp. 25-30, Dec. 2021. | |
| Paper # | RECONF2021-29 | |
| Date of Issue | 2021-11-24 (VLD, ICD, DC, RECONF) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2021-21 ICD2021-31 DC2021-27 RECONF2021-29 Link to ES Tech. Rep. Archives: ICD2021-31 |
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| Conference Information | |
| Committee | VLD DC RECONF ICD IPSJ-SLDM |
| Conference Date | 2021-12-01 - 2021-12-02 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2021 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2021-12-VLD-DC-RECONF-ICD-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Block Sparse MLP-based Vision DNN Accelerators on Embedded FPGAs |
| Sub Title (in English) | |
| Keyword(1) | DNN |
| Keyword(2) | Vision Transformer |
| Keyword(3) | MLP |
| Keyword(4) | gMLP |
| Keyword(5) | FPGA |
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| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Akira Jinguji |
| 1st Author's Affiliation | Tokyo Institute of Technology (Tokyo Tech) |
| 2nd Author's Name | Hiroki Nakahara |
| 2nd Author's Affiliation | Tokyo Institute of Technology (Tokyo Tech) |
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| Speaker | Author-1 |
| Date Time | 2021-12-01 09:20:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | VLD2021-21, ICD2021-31, DC2021-27, RECONF2021-29 |
| Volume (vol) | vol.121 |
| Number (no) | no.277(VLD), no.278(ICD), no.279(DC), no.280(RECONF) |
| Page | pp.25-30 |
| #Pages | 6 |
| Date of Issue | 2021-11-24 (VLD, ICD, DC, RECONF) |
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