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| Presentation | 2022-03-04 11:25 Analysis of Relationship between Communications Forbidden Time Generation Mechanism and THD, odd order and even order THD in Power Line Communications (PLC) system Junya Aoki (Toyo Univ.), Kenji Kita (Daido Univ.), Hiroyasu Ishikawa (Nihon Univ.), Hideyuki Shinonaga (Toyo Univ.)  CAS2021-91 CS2021-93 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The authors have indicated that communications forbidden time not detecting packets occurs when a specific electrical equipment is connected to a power-line, and proposed an instantaneous power-line frequency synchronized superimposed chart as an analysis method of it. Next, we showed that the signal is disturbed when the diode in the full-wave rectifier circuit switched between conduction and non-conduction, and examined the relationship between this phenomenon and the communications forbidden time. In this paper, a full-wave rectifying/smoothing circuit is connected to the power line, and a sine wave representative of the frequency band of high-speed PLC is applied. We evaluate Total Harmonic Distortion of the sine wave and the newly proposed odd order and even order THD, and examine the relationship between the communications forbidden time generation mechanism and THD. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | PLC / Full-Wave Rectifying and Smoothing Circuit / Communications Forbidden Time / Instantaneous Power-Line Frequency Synchronized Superimposed Chart / Packet Capture Analysis / Total Harmonic Distortion / / | |
| Reference Info. | IEICE Tech. Rep., vol. 121, no. 395, CS2021-93, pp. 93-98, March 2022. | |
| Paper # | CS2021-93 | |
| Date of Issue | 2022-02-24 (CAS, CS) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CAS2021-91 CS2021-93 |
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| Conference Information | |
| Committee | CAS CS |
| Conference Date | 2022-03-03 - 2022-03-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Network processor, Signal processing and circuits for communications, Wireless LAN / PAN, etc. |
| Paper Information | |
| Registration To | CS |
| Conference Code | 2022-03-CAS-CS |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Analysis of Relationship between Communications Forbidden Time Generation Mechanism and THD, odd order and even order THD in Power Line Communications (PLC) system |
| Sub Title (in English) | |
| Keyword(1) | PLC |
| Keyword(2) | Full-Wave Rectifying and Smoothing Circuit |
| Keyword(3) | Communications Forbidden Time |
| Keyword(4) | Instantaneous Power-Line Frequency Synchronized Superimposed Chart |
| Keyword(5) | Packet Capture Analysis |
| Keyword(6) | Total Harmonic Distortion |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Junya Aoki |
| 1st Author's Affiliation | Toyo University (Toyo Univ.) |
| 2nd Author's Name | Kenji Kita |
| 2nd Author's Affiliation | Daido University (Daido Univ.) |
| 3rd Author's Name | Hiroyasu Ishikawa |
| 3rd Author's Affiliation | Nihon University (Nihon Univ.) |
| 4th Author's Name | Hideyuki Shinonaga |
| 4th Author's Affiliation | Toyo University (Toyo Univ.) |
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| Speaker | Author-1 |
| Date Time | 2022-03-04 11:25:00 |
| Presentation Time | 25 minutes |
| Registration for | CS |
| Paper # | CAS2021-91, CS2021-93 |
| Volume (vol) | vol.121 |
| Number (no) | no.394(CAS), no.395(CS) |
| Page | pp.93-98 |
| #Pages | 6 |
| Date of Issue | 2022-02-24 (CAS, CS) |
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