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| Presentation | 2022-08-08 16:35 [Invited Talk] A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur Zule Xu, Masaru Osada, Tetsuya Iizuka (UTokyo)  SDM2022-43 ICD2022-11 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We present a type-II fractional-N hybrid switched-capacitor sampling PLL, using a capacitive digital-to-analog converter (CDAC) as a sampler and an analog adder receiving the digital integrator’s output. To guarantee sufficient CDAC settling time and filter switch-on time, we designed a synchronous timing generator utilizing the multi-modulus divider’s (MMDIV’s) inter-stage clocks. The prototype chip in 65-nm CMOS achieves −80-dBc reference spur, 236-fs integrated RMS jitter, and 4.6-mW power consumption, translating to −246-dB FoM. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | hybrid PLL / sampling PLL / fractional-N / CDAC / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 122, no. 149, ICD2022-11, pp. 41-44, Aug. 2022. | |
| Paper # | ICD2022-11 | |
| Date of Issue | 2022-08-01 (SDM, ICD) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SDM2022-43 ICD2022-11 |
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| Conference Information | |
| Committee | ICD SDM ITE-IST |
| Conference Date | 2022-08-08 - 2022-08-10 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2022-08-ICD-SDM-IST |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur |
| Sub Title (in English) | |
| Keyword(1) | hybrid PLL |
| Keyword(2) | sampling PLL |
| Keyword(3) | fractional-N |
| Keyword(4) | CDAC |
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| 1st Author's Name | Zule Xu |
| 1st Author's Affiliation | The University of Tokyo (UTokyo) |
| 2nd Author's Name | Masaru Osada |
| 2nd Author's Affiliation | The University of Tokyo (UTokyo) |
| 3rd Author's Name | Tetsuya Iizuka |
| 3rd Author's Affiliation | The University of Tokyo (UTokyo) |
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| Speaker | Author-1 |
| Date Time | 2022-08-08 16:35:00 |
| Presentation Time | 45 minutes |
| Registration for | ICD |
| Paper # | SDM2022-43, ICD2022-11 |
| Volume (vol) | vol.122 |
| Number (no) | no.148(SDM), no.149(ICD) |
| Page | pp.41-44 |
| #Pages | 4 |
| Date of Issue | 2022-08-01 (SDM, ICD) |
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