Paper Abstract and Keywords |
Presentation |
2022-10-25 10:50
Power current simulation and side channel leakage evaluation of cryptographic IC chips Rikuu Hasegawa, Takuya Wadatsumi, Kazuki Monta, Takuji Miki, Makoto Nagata (Kobe Univ.) HWS2022-32 ICD2022-24 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Cryptographic modules are threatened by side-channel attacks that use side-channel information to decrypt internal confidential information. In this paper, we evaluate the leakage o side-channel information by power current simulation using power libraries and compare it with the leakage of side-channel information measured on a cryptographic module in operation. If simulation-based evaluation becomes possible, side-channel information leakage can be evaluated from the design step of cryptographic modules, which is expected to reduce the cost of design with countermeasures. In this study, a cryptographic module with advanced encryption standard (AES) is used as the evaluation target. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Crypt Modules / Power current simulation / Side-channel leakage / AES / Correlation power analysis / / / |
Reference Info. |
IEICE Tech. Rep., vol. 122, no. 227, HWS2022-32, pp. 12-16, Oct. 2022. |
Paper # |
HWS2022-32 |
Date of Issue |
2022-10-18 (HWS, ICD) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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HWS2022-32 ICD2022-24 |
Conference Information |
Committee |
HWS ICD |
Conference Date |
2022-10-25 - 2022-10-25 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
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(See Japanese page) |
Topics (in English) |
Hardware Security, etc. |
Paper Information |
Registration To |
HWS |
Conference Code |
2022-10-HWS-ICD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Power current simulation and side channel leakage evaluation of cryptographic IC chips |
Sub Title (in English) |
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Keyword(1) |
Crypt Modules |
Keyword(2) |
Power current simulation |
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Side-channel leakage |
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AES |
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Correlation power analysis |
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1st Author's Name |
Rikuu Hasegawa |
1st Author's Affiliation |
Kobe University (Kobe Univ.) |
2nd Author's Name |
Takuya Wadatsumi |
2nd Author's Affiliation |
Kobe University (Kobe Univ.) |
3rd Author's Name |
Kazuki Monta |
3rd Author's Affiliation |
Kobe University (Kobe Univ.) |
4th Author's Name |
Takuji Miki |
4th Author's Affiliation |
Kobe University (Kobe Univ.) |
5th Author's Name |
Makoto Nagata |
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Kobe University (Kobe Univ.) |
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Speaker |
Author-1 |
Date Time |
2022-10-25 10:50:00 |
Presentation Time |
25 minutes |
Registration for |
HWS |
Paper # |
HWS2022-32, ICD2022-24 |
Volume (vol) |
vol.122 |
Number (no) |
no.227(HWS), no.228(ICD) |
Page |
pp.12-16 |
#Pages |
5 |
Date of Issue |
2022-10-18 (HWS, ICD) |
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