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Paper Abstract and Keywords
Presentation 2023-03-02 14:40
[Memorial Lecture] A method for synthesizing quantum circuits satisfying NNA constraints using SMT solvers
Kyehei Seino, Shigeru Yamashita (Ritsumeikan University) VLD2022-94 HWS2022-65
Abstract (in Japanese) (See Japanese page) 
(in English) It is natural to assume that we can perform quantum operations be-
tween only two adjacent physical qubits (quantum bits) to realize

a quantum computer for both the current and possible future tech-
nologies. This restriction is called the Nearest Neighbor Architec-
ture (NNA) restriction. This paper proposes an SMT-solver-based

synthesis of quantum circuits consisting of CNOT, H, and T gates

to satisfy the NNA restriction. Although the existing SMT-solver-
based synthesis cannot treat H and T gates directly, our method

treats the functionality of quantum-specific T and H gates care-
fully so that we can utilize an SMT-solver to minimize the number

of CNOT gates; unlike the existing SMT-solver-based methods, our
method considers “Don’t Care” conditions in intermediate points

of a quantum circuit by exploiting the property of T gates to re-
duce CNOT gates. Experimental results show that our approach

can reduce the number of CNOT gates by 58.11% on average com-
pared to the naive application of the existing method which does

not consider the “Don’t Care” condition.
Keyword (in Japanese) (See Japanese page) 
(in English) Nearest Neighbor Architecture (NNA) restriction / SMT-Solver / T gate / Don’t Care Condition / / / /  
Reference Info. IEICE Tech. Rep., vol. 122, no. 402, VLD2022-94, pp. 112-112, March 2023.
Paper # VLD2022-94 
Date of Issue 2023-02-22 (VLD, HWS) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2022-94 HWS2022-65

Conference Information
Committee HWS VLD  
Conference Date 2023-03-01 - 2023-03-04 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2023-03-HWS-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A method for synthesizing quantum circuits satisfying NNA constraints using SMT solvers 
Sub Title (in English)  
Keyword(1) Nearest Neighbor Architecture (NNA) restriction  
Keyword(2) SMT-Solver  
Keyword(3) T gate  
Keyword(4) Don’t Care Condition  
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Keyword(8)  
1st Author's Name Kyehei Seino  
1st Author's Affiliation Ritsumeikan University (Ritsumeikan University)
2nd Author's Name Shigeru Yamashita  
2nd Author's Affiliation Ritsumeikan University (Ritsumeikan University)
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Speaker Author-1 
Date Time 2023-03-02 14:40:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2022-94, HWS2022-65 
Volume (vol) vol.122 
Number (no) no.402(VLD), no.403(HWS) 
Page p.112 
#Pages 1 
Date of Issue 2023-02-22 (VLD, HWS) 

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