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Paper Abstract and Keywords
Presentation 2023-08-08 11:25
Low-Cost Sorting Network Circuits Based on Temporal Logic Using Single Flux Quantum Circuits
Zeyu Han, Zongyuan Li, Yamanashi Yuki, Yoshikawa Nobuyuki (YNU) SCE2023-5
Abstract (in Japanese) (See Japanese page) 
(in English) Sorting is important in various applications such as image processing and switching systems. Hardware cost and power consumption are the dominant concerns. The usual approach is to wire up a network of compare-and-swap (CAS) units in a Bitonic network, which can be easily pipelined. This paper proposes a novel area-efficient sorting network approach based on Single Flux Quantum (SFQ) temporal logic. In temporal logic, numbers are encoded uniformly by the time of pulse. We designed CAS using two different temporal encoding methods and compared the circuit performance with conventional SFQ logic.
Keyword (in Japanese) (See Japanese page) 
(in English) Sorting Network / Single Flux Quantum Circuits / Temporal Logic / / / / /  
Reference Info. IEICE Tech. Rep., vol. 123, no. 153, SCE2023-5, pp. 22-27, Aug. 2023.
Paper # SCE2023-5 
Date of Issue 2023-08-01 (SCE) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SCE2023-5

Conference Information
Committee SCE  
Conference Date 2023-08-08 - 2023-08-08 
Place (in Japanese) (See Japanese page) 
Place (in English) Yokohama National Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SCE 
Conference Code 2023-08-SCE 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Low-Cost Sorting Network Circuits Based on Temporal Logic Using Single Flux Quantum Circuits 
Sub Title (in English)  
Keyword(1) Sorting Network  
Keyword(2) Single Flux Quantum Circuits  
Keyword(3) Temporal Logic  
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1st Author's Name Zeyu Han  
1st Author's Affiliation Yokohama National University (YNU)
2nd Author's Name Zongyuan Li  
2nd Author's Affiliation Yokohama National University (YNU)
3rd Author's Name Yamanashi Yuki  
3rd Author's Affiliation Yokohama National University (YNU)
4th Author's Name Yoshikawa Nobuyuki  
4th Author's Affiliation Yokohama National University (YNU)
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Speaker Author-1 
Date Time 2023-08-08 11:25:00 
Presentation Time 25 minutes 
Registration for SCE 
Paper # SCE2023-5 
Volume (vol) vol.123 
Number (no) no.153 
Page pp.22-27 
#Pages 6 
Date of Issue 2023-08-01 (SCE) 

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