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Paper Abstract and Keywords
Presentation 2023-11-16 13:20
Tamper Resistance Evaluation on FPGA for Low-Latency Cipher Sonic
Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) VLD2023-49 ICD2023-57 DC2023-56 RECONF2023-52
Abstract (in Japanese) (See Japanese page) 
(in English) Industry 5.0 promotes smart factories for system optimization by utilizing IoT and AI in the industrial field. The smart factory requires high real-time performance to improve the efficiency of production lines and security for confidential data such as corporate know-how and customer information. Therefore, low-latency lightweight block ciphers, which are one of the cryptographic techniques that can both ensure security and suppress the overhead of computational latency, are important elemental technologies for the construction of secure smart factories. Also, it is very important to evaluate the tamper-resistance of cryptographic on real devices due to the reported threat of deep learning side-channel attacks, which learn physical information during hardware implementation and analyze the secret key using deep learning. Therefore, this study evaluates the tamper resistance of Sonic, a state-of-the-art low-latency lightweight block cipher implemented unrolled on FPGAs, against deep learning side-channel attacks. The analysis method uses a Hamming-weighted power model focusing on the AND operations included in Sonic.
Keyword (in Japanese) (See Japanese page) 
(in English) Hardware Security / Lightweight Block Cipher / Side-Channel Attack / Sonic / / / /  
Reference Info. IEICE Tech. Rep., vol. 123, no. 258, VLD2023-49, pp. 101-105, Nov. 2023.
Paper # VLD2023-49 
Date of Issue 2023-11-08 (VLD, ICD, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2023-49 ICD2023-57 DC2023-56 RECONF2023-52

Conference Information
Committee VLD DC RECONF ICD IPSJ-SLDM  
Conference Date 2023-11-15 - 2023-11-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Civic Auditorium Sears Home Yume Hall 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2023 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2023-11-VLD-DC-RECONF-ICD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Tamper Resistance Evaluation on FPGA for Low-Latency Cipher Sonic 
Sub Title (in English)  
Keyword(1) Hardware Security  
Keyword(2) Lightweight Block Cipher  
Keyword(3) Side-Channel Attack  
Keyword(4) Sonic  
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1st Author's Name Shu Takemoto  
1st Author's Affiliation Meijo University (Meijo Univ.)
2nd Author's Name Yusuke Nozaki  
2nd Author's Affiliation Meijo University (Meijo Univ.)
3rd Author's Name Masaya Yoshikawa  
3rd Author's Affiliation Meijo University (Meijo Univ.)
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Speaker Author-1 
Date Time 2023-11-16 13:20:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2023-49, ICD2023-57, DC2023-56, RECONF2023-52 
Volume (vol) vol.123 
Number (no) no.258(VLD), no.259(ICD), no.260(DC), no.261(RECONF) 
Page pp.101-105 
#Pages 5 
Date of Issue 2023-11-08 (VLD, ICD, DC, RECONF) 

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