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Paper Abstract and Keywords
Presentation 2023-11-17 10:25
Low-Latency Hardware Implementation for SPHINCS+ signature generation
Yuta Takeshima, Makoto Ikeda (The Univ. of Tokyo) VLD2023-69 ICD2023-77 DC2023-76 RECONF2023-72
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, research and standardization of post-quantum cryptography have been actively pursued. In 2022, the digital signatures standardized by NIST included three types: CRYSTALS-Dilithium and FALCON, which are classified as lattice-based cryptography, and $text{SPHINCS}^+$, which is classified as a hash-based signature. While the other two rely on the hardness of lattice problems and the difficulty of hash collision detection for their security, $text{SPHINCS}^+$ relies solely on hashes, making it potentially more resistant to breaches. However, its computational cost is higher than the other two, posing challenges for use in scenarios demanding fast communication, such as vehicle-to-vehicle communication. In this study, we examined the number of operators required to achieve latency equivalent to that of CRYSTALS-Dilithium. By running 21 operators in parallel, we demonstrated a potential speed-up of 18.9 times.
Keyword (in Japanese) (See Japanese page) 
(in English) SPHINCS+ / hash-based signature / Post-Quantum Cryptography / hardware / / / /  
Reference Info. IEICE Tech. Rep., vol. 123, no. 258, VLD2023-69, pp. 200-204, Nov. 2023.
Paper # VLD2023-69 
Date of Issue 2023-11-08 (VLD, ICD, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2023-69 ICD2023-77 DC2023-76 RECONF2023-72

Conference Information
Committee VLD DC RECONF ICD IPSJ-SLDM  
Conference Date 2023-11-15 - 2023-11-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Civic Auditorium Sears Home Yume Hall 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2023 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2023-11-VLD-DC-RECONF-ICD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Low-Latency Hardware Implementation for SPHINCS+ signature generation 
Sub Title (in English)  
Keyword(1) SPHINCS+  
Keyword(2) hash-based signature  
Keyword(3) Post-Quantum Cryptography  
Keyword(4) hardware  
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1st Author's Name Yuta Takeshima  
1st Author's Affiliation The University of Tokyo (The Univ. of Tokyo)
2nd Author's Name Makoto Ikeda  
2nd Author's Affiliation The University of Tokyo (The Univ. of Tokyo)
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Speaker Author-1 
Date Time 2023-11-17 10:25:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2023-69, ICD2023-77, DC2023-76, RECONF2023-72 
Volume (vol) vol.123 
Number (no) no.258(VLD), no.259(ICD), no.260(DC), no.261(RECONF) 
Page pp.200-204 
#Pages 5 
Date of Issue 2023-11-08 (VLD, ICD, DC, RECONF) 

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