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Paper Abstract and Keywords
Presentation 2024-02-28 15:55
Three-layer Bottleneck Channel Track Assignment for Pins Placed on Opposite Sides
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Mathieu Molongo, Makoto Minami, Katsuya Nishioka (Jedat) VLD2023-103 HWS2023-63 ICD2023-92
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, for a three-layer bottleneck channel routing problem in which pins of each net are placed on the upper or lower boundary of the routing region, a condition of the pin placement with high feasibility is shown and a routing algorithm for these problem instances is proposed. The proposed algorithm determines the the track and layer assignment of nets by dividing the net set into two parts and running a U-shaped routing algorithm on each part. Physical routing can be obtained if the pin placement satisfies the condition and the algorithm outputs a feasible solution.
Keyword (in Japanese) (See Japanese page) 
(in English) Channel Routing / Three-layer Bottleneck Routing / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 123, no. 390, VLD2023-103, pp. 24-29, Feb. 2024.
Paper # VLD2023-103 
Date of Issue 2024-02-21 (VLD, HWS, ICD) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2023-103 HWS2023-63 ICD2023-92

Conference Information
Committee VLD HWS ICD  
Conference Date 2024-02-28 - 2024-03-02 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2024-02-VLD-HWS-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Three-layer Bottleneck Channel Track Assignment for Pins Placed on Opposite Sides 
Sub Title (in English)  
Keyword(1) Channel Routing  
Keyword(2) Three-layer Bottleneck Routing  
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1st Author's Name Kazuya Taniguchi  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
2nd Author's Name Satoshi Tayu  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
3rd Author's Name Atsushi Takahashi  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
4th Author's Name Mathieu Molongo  
4th Author's Affiliation Jedat (Jedat)
5th Author's Name Makoto Minami  
5th Author's Affiliation Jedat (Jedat)
6th Author's Name Katsuya Nishioka  
6th Author's Affiliation Jedat (Jedat)
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Speaker Author-1 
Date Time 2024-02-28 15:55:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2023-103, HWS2023-63, ICD2023-92 
Volume (vol) vol.123 
Number (no) no.390(VLD), no.391(HWS), no.392(ICD) 
Page pp.24-29 
#Pages 6 
Date of Issue 2024-02-21 (VLD, HWS, ICD) 

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