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Paper Abstract and Keywords
Presentation 2024-03-01 15:55
Hardware Design Based on Full Parameter Support and Parallelism Optimization for Key Encapsulation Mechanism FIPS203
Yuto Nakamura, Makoto Ikeda (UTokyo) VLD2023-131 HWS2023-91 ICD2023-120
Abstract (in Japanese) (See Japanese page) 
(in English) The emergence of quantum computers potentially threatens the security of traditional cryptographic techniques that depend on the difficulty of problems such as factorization and discrete logarithms. In recent years, there has been a movement towards standardizing post-quantum cryptography. In this study, we designed and optimized the parallelism of hardware for multiple parameter sets in key encapsulation mechanisms (KEMs) based on module lattices, in accordance with NIST's FIPS203. As a result of the optimization study, we logically synthesized hardware designed to match the parallelism to the number of columns in the matrices used. In this multi-parameter compatible hardware, we confirmed an area-time efficiency approximately 1.6 times greater than that of previous studies.
Keyword (in Japanese) (See Japanese page) 
(in English) Post-Quantum Cryptography / Key encapsulation mechanism / CRYSTALS-Kyber / FIPS203 / / / /  
Reference Info. IEICE Tech. Rep., vol. 123, no. 391, HWS2023-91, pp. 167-172, Feb. 2024.
Paper # HWS2023-91 
Date of Issue 2024-02-21 (VLD, HWS, ICD) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2023-131 HWS2023-91 ICD2023-120

Conference Information
Committee VLD HWS ICD  
Conference Date 2024-02-28 - 2024-03-02 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
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Paper Information
Registration To HWS 
Conference Code 2024-02-VLD-HWS-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Hardware Design Based on Full Parameter Support and Parallelism Optimization for Key Encapsulation Mechanism FIPS203 
Sub Title (in English)  
Keyword(1) Post-Quantum Cryptography  
Keyword(2) Key encapsulation mechanism  
Keyword(3) CRYSTALS-Kyber  
Keyword(4) FIPS203  
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1st Author's Name Yuto Nakamura  
1st Author's Affiliation The University of Tokyo (UTokyo)
2nd Author's Name Makoto Ikeda  
2nd Author's Affiliation The University of Tokyo (UTokyo)
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Speaker Author-1 
Date Time 2024-03-01 15:55:00 
Presentation Time 25 minutes 
Registration for HWS 
Paper # VLD2023-131, HWS2023-91, ICD2023-120 
Volume (vol) vol.123 
Number (no) no.390(VLD), no.391(HWS), no.392(ICD) 
Page pp.167-172 
#Pages 6 
Date of Issue 2024-02-21 (VLD, HWS, ICD) 

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