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Paper Abstract and Keywords
Presentation 2024-03-02 11:40
eFPGA-based IP Protection of Embedded Processor Design
Tomosuke Ichioka, Tanvir Ahmed, Yuko Hara (Tokyo Tech) VLD2023-139 HWS2023-99 ICD2023-128
Abstract (in Japanese) (See Japanese page) 
(in English) As manufacturing costs continue to grow, IC manufacturers are increasingly outsourcing IC manufacturing to third-party foundries in order to reduce the cost of manufacturing equipment. As a result, problems such as IP theft and unauthorized manufacturing are becoming more serious. This study focuses on IP protection by circuit replacement using eFPGA as a solution to this problem. Assuming a case where IP protection is applied to the circuit design of a processor, we focus on the versatility of the processor and evaluate the effects (i.e., IP protection and circuit overhead) of circuit replacement by eFPGA from the application perspective.
Keyword (in Japanese) (See Japanese page) 
(in English) Embedded FPGA (eFPGA) / IP Protection / SAT Attack / / / / /  
Reference Info. IEICE Tech. Rep., vol. 123, no. 391, HWS2023-99, pp. 209-214, Feb. 2024.
Paper # HWS2023-99 
Date of Issue 2024-02-21 (VLD, HWS, ICD) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2023-139 HWS2023-99 ICD2023-128

Conference Information
Committee VLD HWS ICD  
Conference Date 2024-02-28 - 2024-03-02 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To HWS 
Conference Code 2024-02-VLD-HWS-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) eFPGA-based IP Protection of Embedded Processor Design 
Sub Title (in English)  
Keyword(1) Embedded FPGA (eFPGA)  
Keyword(2) IP Protection  
Keyword(3) SAT Attack  
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1st Author's Name Tomosuke Ichioka  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
2nd Author's Name Tanvir Ahmed  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
3rd Author's Name Yuko Hara  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
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Speaker Author-1 
Date Time 2024-03-02 11:40:00 
Presentation Time 25 minutes 
Registration for HWS 
Paper # VLD2023-139, HWS2023-99, ICD2023-128 
Volume (vol) vol.123 
Number (no) no.390(VLD), no.391(HWS), no.392(ICD) 
Page pp.209-214 
#Pages 6 
Date of Issue 2024-02-21 (VLD, HWS, ICD) 

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