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Paper Abstract and Keywords
Presentation 2024-04-12 11:25
Implementation and Preliminary Evaluation of an FPGA-based Network Switch Supporting Credit-based Shaper for Time Sensitive Networks
Akram Ben Ahmed, Takahiro Hirofuchi, Takaaki Fukai (AIST) NS2024-11
Abstract (in Japanese) (See Japanese page) 
(in English) Time Sensitive Networking (TSN) is a set of novel open standards that aims to provide deterministic, reliable, high-bandwidth and low-latency communication. It is expected to be the backbone of future communication in industrial critical applications. In this paper, we present our work in progress to prototype an FPGA-based network switch supporting Credit Based Shaper for Time Sensitive Networking. We discuss the different hardware implementation aspects of the proposed switch and the preliminary evaluation results to validate our proposal. Our evaluations show that the proposed switch properly shapes the traffic by smoothing out irregular traffics and efficiently forwarding prioritize traffic according to the CBS protocols rules. In addition, we demonstrate that our hardware latency evaluation results are conform with the CBS theoretical model.
Keyword (in Japanese) (See Japanese page) 
(in English) Time Sensitive Networks / Credit Based Shaper / FPGA / Switch Architecture / / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 2, NS2024-11, pp. 47-52, April 2024.
Paper # NS2024-11 
Date of Issue 2024-04-04 (NS) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF NS2024-11

Conference Information
Committee NS  
Conference Date 2024-04-11 - 2024-04-12 
Place (in Japanese) (See Japanese page) 
Place (in English) Okayama Prefectural Library + Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Communication traffic theory, Traffic and quality evaluation, Network performance evaluation, QoS/QoE, Reliability and robustness, Traffic and quality management, AI and machine learning, Network and system operation management, High capacity, low latency, many connections, General 
Paper Information
Registration To NS 
Conference Code 2024-04-NS 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementation and Preliminary Evaluation of an FPGA-based Network Switch Supporting Credit-based Shaper for Time Sensitive Networks 
Sub Title (in English)  
Keyword(1) Time Sensitive Networks  
Keyword(2) Credit Based Shaper  
Keyword(3) FPGA  
Keyword(4) Switch Architecture  
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1st Author's Name Akram Ben Ahmed  
1st Author's Affiliation National Institute of Advanced Industrial Science and Technology (AIST)
2nd Author's Name Takahiro Hirofuchi  
2nd Author's Affiliation National Institute of Advanced Industrial Science and Technology (AIST)
3rd Author's Name Takaaki Fukai  
3rd Author's Affiliation National Institute of Advanced Industrial Science and Technology (AIST)
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Speaker Author-1 
Date Time 2024-04-12 11:25:00 
Presentation Time 25 minutes 
Registration for NS 
Paper # NS2024-11 
Volume (vol) vol.124 
Number (no) no.2 
Page pp.47-52 
#Pages 6 
Date of Issue 2024-04-04 (NS) 

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