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Paper Abstract and Keywords
Presentation 2024-06-10 16:20
Rapid Inter-Thread Communication Using Message Passing Unit in RISC-V SMT Processor
Go Akamatsu, Shogo Takata, Tomoaki Tanaka, Hironori Nakajo (TUAT) CPSY2024-3 DC2024-3 RECONF2024-3
Abstract (in Japanese) (See Japanese page) 
(in English) In this study, a new inter-thread communication method was implemented on the RISC-V SMT processor with the aim of reducing the overhead in inter-thread communication when using multi-threading. As a background to this research, the conventional inter-thread communication using the A-extension instruction has a large overhead associated with judging the execution result and re-issuing the instruction when it fails. Therefore, this research aimed to construct an efficient communication method that replaces the A-extension instruction. A new hardware named message passing unit was added to the RISC-V SMT processor implemented in our laboratory. This unit transfers data using data transfer requests and receive requests issued by each thread. This hardware reduces the overhead of inter-thread communication without using the main memory. The performance evaluation used a matrix multiplication programs and compared the performance of the message-passing mechanism and the A-extension in simulation. The results showed that the message passing unit achieved a speed-up by up to 3.4 times compared to the A-extension.
Keyword (in Japanese) (See Japanese page) 
(in English) RISC-V / Multithreading / SMT / Inter-thread communication / / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 72, CPSY2024-3, pp. 12-17, June 2024.
Paper # CPSY2024-3 
Date of Issue 2024-06-03 (CPSY, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2024-3 DC2024-3 RECONF2024-3

Conference Information
Committee CPSY DC RECONF IPSJ-ARC  
Conference Date 2024-06-10 - 2024-06-12 
Place (in Japanese) (See Japanese page) 
Place (in English) Isawa View Hotel 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Architecture, Computer Systems, Dependable Computing, Reconfigurable System, etc. 
Paper Information
Registration To CPSY 
Conference Code 2024-06-CPSY-DC-RECONF-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Rapid Inter-Thread Communication Using Message Passing Unit in RISC-V SMT Processor 
Sub Title (in English)  
Keyword(1) RISC-V  
Keyword(2) Multithreading  
Keyword(3) SMT  
Keyword(4) Inter-thread communication  
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1st Author's Name Go Akamatsu  
1st Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
2nd Author's Name Shogo Takata  
2nd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
3rd Author's Name Tomoaki Tanaka  
3rd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
4th Author's Name Hironori Nakajo  
4th Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
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Speaker Author-1 
Date Time 2024-06-10 16:20:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2024-3, DC2024-3, RECONF2024-3 
Volume (vol) vol.124 
Number (no) no.72(CPSY), no.73(DC), no.74(RECONF) 
Page pp.12-17 
#Pages 6 
Date of Issue 2024-06-03 (CPSY, DC, RECONF) 

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