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Paper Abstract and Keywords
Presentation 2024-06-10 17:10
Preliminary Report on an FPGA-based Prototype of a Network Switch Supporting Asynchronous Traffic Shaping for Time Sensitive Networking
Akram Ben Ahmed, Takahiro Hirofuchi, Takaaki Fukai (AIST) CPSY2024-5 DC2024-5 RECONF2024-5
Abstract (in Japanese) (See Japanese page) 
(in English) Time Sensitive Networking (TSN) is an additional set of new open standards to conventional IEEE 802.3 Ethernet networks that aims to provide deterministic, reliable, high-bandwidth and low-latency communication.
In this paper, we present an initial architecture of an FPGA-based network switch supporting Asynchronous Traffic Shaping (ATS) for Time Sensitive Networking. We present the key architectural components and implementation aspects of the proposed switch and discuss the preliminary evaluation results in a fair amount of details to validate our proposal. The conducted experiments confirm that the proposed switch executes the proper burst and rate control management, and that our arrival rate and arrival frame interval evaluation results are conform with the ATS theoretical model.
Keyword (in Japanese) (See Japanese page) 
(in English) Time Sensitive Networks / Asynchronous Traffic Shaping, / FPGA / Switch Architecture / / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 74, RECONF2024-5, pp. 23-29, June 2024.
Paper # RECONF2024-5 
Date of Issue 2024-06-03 (CPSY, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2024-5 DC2024-5 RECONF2024-5

Conference Information
Committee CPSY DC RECONF IPSJ-ARC  
Conference Date 2024-06-10 - 2024-06-12 
Place (in Japanese) (See Japanese page) 
Place (in English) Isawa View Hotel 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Architecture, Computer Systems, Dependable Computing, Reconfigurable System, etc. 
Paper Information
Registration To RECONF 
Conference Code 2024-06-CPSY-DC-RECONF-ARC 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Preliminary Report on an FPGA-based Prototype of a Network Switch Supporting Asynchronous Traffic Shaping for Time Sensitive Networking 
Sub Title (in English)  
Keyword(1) Time Sensitive Networks  
Keyword(2) Asynchronous Traffic Shaping,  
Keyword(3) FPGA  
Keyword(4) Switch Architecture  
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1st Author's Name Akram Ben Ahmed  
1st Author's Affiliation National Institute of Advanced Industrial Science and Technology (AIST)
2nd Author's Name Takahiro Hirofuchi  
2nd Author's Affiliation National Institute of Advanced Industrial Science and Technology (AIST)
3rd Author's Name Takaaki Fukai  
3rd Author's Affiliation National Institute of Advanced Industrial Science and Technology (AIST)
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Speaker Author-1 
Date Time 2024-06-10 17:10:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # CPSY2024-5, DC2024-5, RECONF2024-5 
Volume (vol) vol.124 
Number (no) no.72(CPSY), no.73(DC), no.74(RECONF) 
Page pp.23-29 
#Pages 7 
Date of Issue 2024-06-03 (CPSY, DC, RECONF) 

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