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Paper Abstract and Keywords
Presentation 2024-06-11 13:15
Burst Length Optimization in MLC PCM using Encoding and Merge Sort
Jin Lei, Kazuteru Namba (Chiba Univ.) CPSY2024-10 DC2024-10 RECONF2024-10
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, with the development of fields such as big data, artificial intelligence (AI), and the Internet of Things (IoT), demands for data storage and processing have significantly increased. Traditional memory technologies have been revealed to have limitations in terms of read/write speed, durability, and power consumption. Phase Change Memory (PCM), especially Multi-Level Cell (MLC) PCM, is considered a critical area of research to address these challenges. This paper specifically focuses on the read/write speeds of MLC PCM and proposes methods to reduce the number of write operations. We introduced two additional optimizations: pre-encoding of data and optimization of memory control, aimed at further reducing write latency. Experimental results demonstrate that our proposed method significantly enhances the lifespan of PCM compared to the Data Comparison Write (DCW) method, which utilizes only a few metadata bits. Additionally, our method reduces bit flips and increases write efficiency, thereby improving write throughput by up to 20% over DCW. Furthermore, it reduces the dynamic energy required for writing by up to 30% compared to DCW.
Keyword (in Japanese) (See Japanese page) 
(in English) Phase Change Memory (PCM) / Multi level cell (MLC) / Gem5 / / / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 73, DC2024-10, pp. 52-57, June 2024.
Paper # DC2024-10 
Date of Issue 2024-06-03 (CPSY, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2024-10 DC2024-10 RECONF2024-10

Conference Information
Committee CPSY DC RECONF IPSJ-ARC  
Conference Date 2024-06-10 - 2024-06-12 
Place (in Japanese) (See Japanese page) 
Place (in English) Isawa View Hotel 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Architecture, Computer Systems, Dependable Computing, Reconfigurable System, etc. 
Paper Information
Registration To DC 
Conference Code 2024-06-CPSY-DC-RECONF-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Burst Length Optimization in MLC PCM using Encoding and Merge Sort 
Sub Title (in English)  
Keyword(1) Phase Change Memory (PCM)  
Keyword(2) Multi level cell (MLC)  
Keyword(3) Gem5  
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1st Author's Name Jin Lei  
1st Author's Affiliation Chiba University (Chiba Univ.)
2nd Author's Name Kazuteru Namba  
2nd Author's Affiliation Chiba University (Chiba Univ.)
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Speaker Author-1 
Date Time 2024-06-11 13:15:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # CPSY2024-10, DC2024-10, RECONF2024-10 
Volume (vol) vol.124 
Number (no) no.72(CPSY), no.73(DC), no.74(RECONF) 
Page pp.52-57 
#Pages 6 
Date of Issue 2024-06-03 (CPSY, DC, RECONF) 

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