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Paper Abstract and Keywords
Presentation 2024-06-11 11:10
A LBIST Method for Detecting Fault Locations in AI Accelerators
Zhang Jiaxi, Namba Kazuteru (Chiba Univ) CPSY2024-9 DC2024-9 RECONF2024-9
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, artificial intelligence (AI) technology has been widely utilized in various fields such as healthcare, transportation, and logistics, becoming an indispensable part of society and daily life. With the advancement of AI technology, the importance of AI chips has also increased. These chips require special hardware architectures to efficiently perform complex computations that traditional CPU chips cannot handle. Therefore, the detection of AI chips has become increasingly important. In this study, we propose an LBIST (Logic Built-In Self-Test) scheme to identify the specific locations of faulty Process Elements (PEs) for the reliability detection of AI accelerators based on the Systolic Array architecture by combining techniques such as TPG (Test Pattern Generation) using one-hot encoding, the detection rate for stuck-at-0 faults can reach nearly 100%. Moreover, this research examines optimal partitioning algorithms for Systolic Arrays of different sizes to achieve precise PE detection capability.
Keyword (in Japanese) (See Japanese page) 
(in English) AI accelerator / LBIST / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 73, DC2024-9, pp. 46-51, June 2024.
Paper # DC2024-9 
Date of Issue 2024-06-03 (CPSY, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2024-9 DC2024-9 RECONF2024-9

Conference Information
Committee CPSY DC RECONF IPSJ-ARC  
Conference Date 2024-06-10 - 2024-06-12 
Place (in Japanese) (See Japanese page) 
Place (in English) Isawa View Hotel 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Architecture, Computer Systems, Dependable Computing, Reconfigurable System, etc. 
Paper Information
Registration To DC 
Conference Code 2024-06-CPSY-DC-RECONF-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A LBIST Method for Detecting Fault Locations in AI Accelerators 
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Keyword(1) AI accelerator  
Keyword(2) LBIST  
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1st Author's Name Zhang Jiaxi  
1st Author's Affiliation Chiba University (Chiba Univ)
2nd Author's Name Namba Kazuteru  
2nd Author's Affiliation Chiba University (Chiba Univ)
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Speaker Author-1 
Date Time 2024-06-11 11:10:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # CPSY2024-9, DC2024-9, RECONF2024-9 
Volume (vol) vol.124 
Number (no) no.72(CPSY), no.73(DC), no.74(RECONF) 
Page pp.46-51 
#Pages 6 
Date of Issue 2024-06-03 (CPSY, DC, RECONF) 

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