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Paper Abstract and Keywords
Presentation 2024-07-19 14:15
Operable Time Evaluation of FPGA-based Sensor Node with Capacitor Power Supply Varying Basic Circuit Resources
Itsuki Fukumitsu, Akira Yamawaki (Kyutech) CAS2024-22 VLD2024-22 SIP2024-39 MSS2024-22
Abstract (in Japanese) (See Japanese page) 
(in English) We propose a low-power and maintenance-free wireless-wired hierarchical sensor network using zero standby power sensor nodes powered by capacitors. In addition, we use FPGAs in the body of the sensor nodes to achieve advanced information processing in the nodes. The power consumption of FPGA depends on the circuit size. Therefore, in this study, we design a circuit that can arbitrarily change the number of FFs and LUTs, which are basic circuit resources of FPGA, and evaluate the effect of their increase on the operable time of the FPGA node. As a result, the operable time decreased as the number of FFs increased. However, when the capacitor capacitance was 10.0F, the sensor node could operate for 508 seconds even when 20,000 FFs were used. The increase in LUTs had almost no effect on the operation duration, decreasing it by 2.25% at most.
Keyword (in Japanese) (See Japanese page) 
(in English) Wireless Sensor Network / FPGA / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 110, CAS2024-22, pp. 117-121, July 2024.
Paper # CAS2024-22 
Date of Issue 2024-07-11 (CAS, VLD, SIP, MSS) 
ISSN Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CAS2024-22 VLD2024-22 SIP2024-39 MSS2024-22

Conference Information
Committee VLD CAS SIP MSS  
Conference Date 2024-07-18 - 2024-07-19 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
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Paper Information
Registration To CAS 
Conference Code 2024-07-VLD-CAS-SIP-MSS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Operable Time Evaluation of FPGA-based Sensor Node with Capacitor Power Supply Varying Basic Circuit Resources 
Sub Title (in English)  
Keyword(1) Wireless Sensor Network  
Keyword(2) FPGA  
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1st Author's Name Itsuki Fukumitsu  
1st Author's Affiliation Kyushu Institute of Technology (Kyutech)
2nd Author's Name Akira Yamawaki  
2nd Author's Affiliation Kyushu Institute of Technology (Kyutech)
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Speaker Author-1 
Date Time 2024-07-19 14:15:00 
Presentation Time 25 minutes 
Registration for CAS 
Paper # CAS2024-22, VLD2024-22, SIP2024-39, MSS2024-22 
Volume (vol) vol.124 
Number (no) no.110(CAS), no.111(VLD), no.112(SIP), no.113(MSS) 
Page pp.117-121 
#Pages 5 
Date of Issue 2024-07-11 (CAS, VLD, SIP, MSS) 

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